IP Library Granted Patent US 9,911,813
Granted Patent B2
US 9,911,813 · App. 14/651,012 · Granted Mar 6, 2018

Reducing leakage current in semiconductor devices

Inventors: Bin Lu (Boston, MA); Elison de Nazareth Matioli (Cambridge, MA); Tomas Apostol Palacios (Belmont, MA)
Assignee: Massachusetts Institute of Technology
H01L29/267H01L21/0254H01L21/02381H01L21/30604H01L21/8258H01L29/0649H01L29/0688H01L29/1033H01L29/1079H01L29/2003H01L29/7786H01L29/78
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Quick Facts
Patent No.
US 9,911,813
App. No.
14/651,012
Granted
Mar 6, 2018
Kind
B2
Abstract

A semiconductor device includes a first region having a first semiconductor material and a second region having a second semiconductor material. The second region is formed over the first region. The semiconductor device also includes a current blocking structure formed in the first region between first and second terminals of the semiconductor device. The current blocking structure is configured to reduce current flow in the first region between the first and second terminals.

Claims (24)

1. A semiconductor device, comprising:

a first semiconductor region that is a silicon region;

a second semiconductor region comprising a nitride semiconductor material, the second semiconductor region being formed over the silicon region;

first and second terminals of the semiconductor device over the second semiconductor region; and

at least one p-n junction formed in the silicon region between the first and second terminals, the at least one p-n junction being configured to reduce lateral current flow in the silicon region between the first and second terminals.

2. The semiconductor device of claim 1 , wherein the at least one p-n junction comprises a first p-n junction that extends in a direction perpendicular to an interface between the silicon region and the second semiconductor region.

3. The semiconductor device of claim 1 , wherein a third terminal is formed in the silicon region and the at least one p-n junction is further configured to reduce current flow between the third terminal and the first terminal.

4. The semiconductor device of claim 1 , wherein the silicon region is at least a portion of a substrate, the substrate being a bulk semiconductor substrate or a semiconductor-on insulator-substrate.

5. The semiconductor device of claim 1 , wherein the at least one p-n junction extends to an interface between the silicon region and the second semiconductor region.

6. The semiconductor device of claim 1 , wherein the at least one p-n junction is configured to reduce current flow in the silicon region along a direction perpendicular to the interface between the silicon region and the second semiconductor region.

7. The semiconductor device of claim 1 , wherein a p-type region and an n-type region form the at least one p-n junction.

8. The semiconductor device of claim 7 , wherein the p-type region and the n-type region are arranged as stripes.

9. The semiconductor device of claim 1 , wherein the at least one p-n junction comprises a plurality of p-n junctions.

10. The semiconductor device of claim 1 , wherein the semiconductor device is a transistor, wherein the first terminal is a drain terminal of the transistor, and wherein the second terminal is a source terminal of the transistor.

11. A semiconductor device, comprising:

a silicon region;

semiconductor pillars disposed over the silicon region between first and second terminals of the semiconductor device;

an insulating region between the semiconductor pillars to reduce leakage current between the semiconductor pillars; and

a semiconductor region comprising a nitride semiconductor material, the semiconductor region being formed over the semiconductor pillars.

12. The semiconductor device of claim 11 , wherein the insulating region comprises a dielectric material.

13. The semiconductor device of claim 12 , wherein the dielectric material comprises a dielectric fluid.

14. The semiconductor device of claim 12 , wherein the dielectric material comprises at least one of AN, SiN, SiC, polycrystalline diamond, SiO 2 , or another dielectric material with a critical electric field higher than 30 kV/cm.

15. The semiconductor device of claim 11 , wherein the semiconductor pillars comprise silicon.

16. The semiconductor device of claim 11 , wherein adjacent semiconductor pillars are separated from one another by no more than 20 μm.

Assignments (2)
CONFIRMATORY LICENSE Recorded Jan 11, 2024
From: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
To: U.S. DEPARTMENT OF ENERGY
Reel/Frame 066272/0142 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2015
From: LU, BIN; DE NAZARETH MATIOLI, ELISON; PALACIOS, TOMAS APOSTOL
To: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
Reel/Frame 036148/0930 →
Continuity (3)
Provisional Application 61735604 · Dec 11, 2012
Related Publication 20150318360A1 · Nov 5, 2015
Related Publication 20160133710A9 · May 12, 2016