FinFET contact structure and method for forming the same

1. A device comprising:

a substrate comprising a first portion and a second portion separated by an isolation region;

a first gate structure over the first portion;

a first drain/source region and a second drain/source region in the first portion and on opposite sides of the first gate structure, wherein the first drain/source region and the second drain/source region have first concave upper surfaces;

a second gate structure over the second portion; and

a third drain/source region and a fourth drain/source region in the second portion and on opposite sides of the second gate structure, wherein the third drain/source region and the fourth drain/source region have second concave upper surfaces.

2. The device of claim 1 , further comprising:

the first drain/source region, the second drain/source region and the first gate structure form an n-type transistor; and

the third drain/source region, the fourth drain/source region and the second gate structure form a p-type transistor.

3. The device of claim 2 , further comprising:

a first dislocation plane underlying the first drain/source region; and

a second dislocation plane underlying the second drain/source region, wherein the first dislocation plane and the second dislocation plane are parallel to each other.

4. The device of claim 1 , further comprising:

a first drain/source contact in a first recess over the first drain/source region;

a second drain/source contact in a second recess over the second drain/source region;

a third drain/source contact in a third recess over the third drain/source region; and

a fourth drain/source contact in a fourth recess over the fourth drain/source region.

5. The device of claim 4 , wherein:

bottoms of the first recess, the second recess, the third recess and the fourth recess have concave surfaces.

6. The device of claim 4 , wherein:

the first recess, the second recess, the third recess and the fourth recess have a depth in a range from about 5 nm to about 25 nm.

7. The device of claim 1 , wherein:

the isolation region is a shallow trench isolation structure.

8. A device comprising:

an n-type transistor comprising a first gate structure, a first drain/source region and a second drain/source region formed in a first portion of a substrate, wherein the first drain/source region and the second drain/source region have nonplanar top surfaces;

a p-type transistor comprising a second gate structure, a third drain/source region and a fourth drain/source region formed in a second portion of the substrate, wherein the third drain/source region and the fourth drain/source region have nonplanar top surfaces, and wherein the first portion and the second portion are separated by an isolation region;

a first drain/source contact in a first recess over the first drain/source region;

a second drain/source contact in a second recess over the second drain/source region;

a third drain/source contact in a third recess over the third drain/source region; and

a fourth drain/source contact in a fourth recess over the fourth drain/source region.

9. The device of claim 8 , further comprising:

a first dislocation plane underlying the first drain/source region; and

a second dislocation plane underlying the second drain/source region.

10. The device of claim 9 , wherein:

the first dislocation plane and the second dislocation plane are parallel to each other.

11. The device of claim 8 , wherein:

a width of the first recess is substantially equal to a width of the first drain/source region.

12. The device of claim 8 , wherein:

a width of the first drain/source region is greater than a width of the first recess.

13. The device of claim 8 , wherein:

the first drain/source region has a first concave top surface; and

the third drain/source region has a second concave top surface.

14. The device of claim 8 , wherein:

a center portion of the first drain/source region has a concave top surface; and

an edge portion of the first drain/source region has a planar top surface.

15. The device of claim 8 , wherein:

a depth of the first recess is in a range from about 5 nm to about 25 nm.

16. A device comprising:

a first drain/source region formed over a first fin line and between a first gate region and a second gate region, wherein each of the first gate region and the second gate region surrounds the first fin line on three sides, wherein the first gate region and the second gate region are separated by an insulation region; and

a second drain/source region formed over a second fin line and between the first gate region and the second gate region, wherein:

the second drain/source region is immediately adjacent to the first drain/source region; and

the first drain/source region and the second drain/source region have nonplanar surfaces.

17. The device of claim 16 , wherein:

the first drain/source region has a first concave upper surface; and

the second drain/source region has a second concave upper surface.

18. The device of claim 16 , further comprising:

a third drain/source region formed over a third fin line and between the first gate region and the second gate region, wherein the third drain/source region is immediately adjacent to the second drain/source region.

19. The device of claim 18 , wherein:

the third drain/source region has a third concave upper surface.

20. The device of claim 18 , wherein:

the first drain/source region, the second drain/source region and the third drain/source region merge to form a merged drain/source region, wherein the merged drain/source region has a concave upper surface.