IP Library Granted Patent US 9,917,096
Granted Patent B2
US 9,917,096 · App. 14/633,405 · Granted Mar 13, 2018

Semiconductor memory device and method for manufacturing same

Inventor: Takeshi Kamigaichi (Yokkaichi, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L27/11582H01L21/28282H01L29/45H01L29/495H01L29/7926
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Quick Facts
Patent No.
US 9,917,096
App. No.
14/633,405
Granted
Mar 13, 2018
Kind
B2
Abstract

According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers and a plurality of inter-layer insulating layers each provided between the plurality of electrode layers; and a columnar portion penetrating the stacked body and extending in a stacking direction of the stacked body. The columnar portion includes a channel body extending in the stacking direction; and a charge storage film provided between the channel body and each of the electrode layers. Each of the electrode layers includes an edge portion provided closer on a central axis side of the columnar portion than the inter-layer insulating layers. The charge storage film covers the edge portion of each of the electrode layers and separated from each other in the stacking direction.

Claims (25)

1. A semiconductor memory device comprising:

a stacked body including a plurality of electrode layers separated by a plurality of inter-layer insulating layers in a stacking direction;

a semiconductor body extending in the stacking direction through the stacked body, the semiconductor body having end portions provided in the stacking direction between the plurality of electrode layers, the end portions of the semiconductor body projecting from a central axis side of the semiconductor body toward an outer side of the semiconductor body;

source layers and insulating films, wherein the insulating films protrude through the plurality of inter-layer insulating layers and are provided opposite to the end portions between the end portions and the source layers; and

a charge storage film discontinuously provided between the semiconductor body and the plurality of electrode layers without overlapping said end portions in the stacking direction, said charge storage film including storage film portions separated via the end portions of the semiconductor body.

2. The device according to claim 1 , wherein the charge storage film is covered with the semiconductor body.

3. The device according to claim 1 , wherein a corner of an edge portion of the plurality of electrode layers is covered with the charge storage film.

4. The device according to claim 1 , wherein the plurality of electrode layers include at least any of tungsten and molybdenum.

5. A method for manufacturing a semiconductor memory device comprising:

forming, on a substrate, a stacked body including a plurality of first layers and a plurality of second layers, the plurality of first layers separately stacked on each other, the plurality of second layers provided between the plurality of first layers;

forming a hole penetrating the stacked body and extending in a stacking direction of the stacked body;

causing a side surface of the second layers to be recessed through the hole and exposing an edge portion of the first layers in a side wall of the hole;

forming, through the hole, a film including a charge storage film on the edge portion of the first layers and the side surface of the second layers;

forming a semiconductor body on an inner side of the film including the charge storage film;

forming a trench penetrating the stacked body and extending in the stacking direction;

removing the second layers through the trench to form a cavity exposing a side surface of the film including the charge storage film; and

removing, through the trench, the film including the charge storage film exposed in the cavity.

6. The method according to claim 5 , further comprising forming an insulating layer on an inner wall of the trench and leaving the cavity between the plurality of the first layers.

7. The method according to claim 5 , further comprising forming, through the trench, an insulating film in the cavity.

8. The method according to claim 5 , further comprising forming the charge storage film covering the edge portion of the first layers.

9. The method according to claim 5 , further comprising forming a projecting portion of the semiconductor body projecting between the plurality of the first layers.

10. The method according to claim 5 , further comprising:

forming an insulating layer in the trench; and

embedding, on an inner side of the insulating layer, a film having conductivity and electrically connected with the substrate to form a source layer.

11. The method according to claim 5 , wherein at least any of a silicon oxide film and a silicon nitride film is used for the plurality of second layers.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043355/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 2, 2015
From: KAMIGAICHI, TAKESHI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 036716/0433 →
Continuity (2)
Provisional Application 62048410 · Sep 10, 2014
Related Publication 20160071871A1 · Mar 10, 2016