Doherty amplifiers with minimum phase output networks

1. An amplifier comprising:

a device package configured to be connected to a printed circuit board (PCB), wherein the device package is distinct from the PCB, and the device package includes

first, second, third, and fourth input leads,

first, second, third, and fourth output leads,

a first amplifier path connected between the first input lead and the first output lead, wherein the first amplifier path includes a first input matching network coupled to the first input lead, and a first amplifier stage coupled between the first input matching network, and the first output lead, and wherein the first amplifier stage forms a portion of a main amplifier path of a Doherty amplifier,

a second amplifier path connected between the second input lead and the second output lead, wherein the second amplifier path includes a second input matching network coupled to the second input lead, and a second amplifier stage coupled between the second input matching network, and the second output lead, and wherein the second amplifier stage forms a portion of a first peaking amplifier path of the Doherty amplifier,

a third amplifier path connected between the third input lead and the third output lead, wherein the third amplifier path includes a third input matching network coupled to the third input lead, and a third amplifier stage coupled between the third input matching network, and the third output lead, and wherein the third amplifier stage forms a portion of a second peaking amplifier path of the Doherty amplifier, and

a fourth amplifier path connected between the fourth input lead and the fourth output lead, wherein the fourth amplifier path includes a fourth input matching network coupled to the fourth input lead, and a fourth amplifier stage coupled between the fourth input matching network, and the fourth output lead, and wherein the fourth amplifier stage forms a portion of a third peaking amplifier path of the Doherty amplifier.

2. The amplifier of claim 1 , further comprising:

an output combining network connected to the PCB, wherein the output combining network includes four combining network inputs, multiple summing nodes, and a combining network output, and the output combining network is configured to combine signals received at the four combining network inputs into a combined signal that is provided at the combining network output;

a first output matching network connected to the PCB and electrically connected between the first output lead and a first combining network input of the four combining network inputs, wherein the first output matching network imparts a phase delay of 90 degrees and provides a single impedance inversion to a first RF signal produced at the first output lead;

a second output matching network connected to the PCB and electrically connected between the second output lead and a second combining network input of the four combining network inputs, wherein the first output matching network imparts a phase delay of 90 degrees and provides a single impedance inversion to a second RF signal produced at the second output lead;

a third output matching network connected to the PCB and electrically connected between the third output lead and a third combining network input of the four combining network inputs, wherein the first output matching network imparts a phase delay of 90 degrees and provides a single impedance inversion to a third RF signal produced at the third output lead;

a fourth output matching network connected to the PCB and electrically connected between the fourth output lead and a fourth combining network input of the four combining network inputs, wherein the first output matching network imparts a phase delay of 90 degrees and provides a single impedance inversion to a fourth RF signal produced at the fourth output lead, and

wherein the multiple summing nodes of the output combining network include a final summing node and two intermediate summing nodes, wherein the final summing node is coupled to the combining network output and is directly coupled to the first combining network input, the two intermediate summing nodes each are directly coupled to a different one of two other combining network inputs of the four combining network inputs, and

wherein the output combining network further includes two impedance transformers each coupled between different sets of adjacent summing nodes of the multiple summing nodes, and an offset line coupled between the lowest-order combining network input and a lowest-order summing node of the two intermediate summing nodes.

3. The amplifier of claim 1 , further comprising:

a four-way power divider connected to the PCB, wherein the four-way power divider includes a power divider input and four power divider outputs, wherein each of the four power divider outputs is coupled to one of the first, second, third, and fourth input leads, and the four-way power divider is configured to divide an input power of an input RF signal received at the power divider input into four portions of the input RF signal, and to provide the four portions of the input RF signal to the four power divider outputs.

4. The amplifier of claim 3 , wherein the four-way power divider further includes a plurality of delay line elements, which impart various phase delays to the four portions of the input RF signal, wherein, starting with a lowest-order delay line element that is coupled to an input to a lowest-order peaking amplifier path, successively higher-order delay line elements each impart an additional 90 degree phase delay to the portions of the input RF signal received by each of the delay line elements.

5. The amplifier of claim 1 , further comprising four input matching networks, wherein each of the four input matching networks is coupled to a different one of the first, second, third, and fourth input leads.

6. The amplifier of claim 1 , wherein the output combining network further includes an additional impedance transformer coupled between the final summing node and the combining network output.