Integrated voltage regulators with magnetically enhanced inductors
Magnetically enhanced inductors integrated with microelectronic devices at chip-level. In embodiments, magnetically enhanced inductors include a through substrate vias (TSVs) with fill metal to carry an electrical current proximate to a magnetic layer disposed on a substrate through which the TSV passes. In certain magnetically enhanced inductor embodiments, a TSV fill metal is disposed within a magnetic material lining the TSV. In certain magnetically enhanced inductor embodiments, a magnetically enhanced inductor includes a plurality of interconnected TSVs disposed proximate to a magnetic material layer on a side of a substrate. In embodiments, voltage regulation circuitry disposed on a first side of a substrate is integrated with one or more magnetically enhanced inductors utilizing a TSV passing through the substrate. In further embodiments, integrated circuitry on a same substrate as the magnetically enhanced inductor, or on another substrate stacked thereon, completes the VR and/or is powered by the VR circuitry.
1. A microelectronic device, comprising: an integrated circuit (IC) disposed on a substrate, wherein the substrate is a silicon substrate; a magnetically enhanced inductor entirely disposed in the substrate and electrically coupled to the IC, wherein the inductor further comprises: a through substrate via (TSV) extending through the substrate; and a magnetic material disposed over a surface of the substrate, adjacent to a conductive length of the inductor; wherein the TSV is a magnetic TSV (MTSV) with the magnetic material forming a liner on sidewalls of the TSV with a conductive fill metal disposed within the magnetic liner and with an intervening dielectric liner there between.
2. The device of claim 1 , wherein a length of a single MTSV defines a total conductive length of the inductor extending adjacent the magnetic material to form an inductor without needing to form turns along the conductive length.
3. The device of claim 1 , wherein the fill metal has a diameter between 5 and 20 jam, and the magnetic material liner has a thickness between 0.5 and 1.5 pm.
4. The device of claim 1 , wherein the magnetic material is disposed on a first side of the substrate, wherein the TSV is one of at least a pair of TSVs coupled in series by a first interconnect metallization disposed over the magnetic material to form a three-dimensional coil.
5. The device of claim 4 , wherein the IC is disposed on a frontside of the substrate, wherein the magnetic material is disposed on a backside of the substrate, and wherein the first interconnect metallization comprises a redistribution metallization layer.
6. The device of claim 4 , wherein the substrate has a thickness less than 100 μm, and wherein the magnetic material has a thickness no greater than 10 μm.
7. The device of claim 6 , wherein the magnetic material comprises a stack having a plurality of magnetic material layers, wherein adjacent magnetic material layers within the stack are spaced apart by an intervening dielectric layer.
8. The device of claim 1 , wherein the IC further comprises:
a power supply circuit electrically coupled to a first end of the inductor; and a load circuit electrically coupled to a second end of the inductor to be powered by the power supply circuit.
9. A microelectronic device, comprising: a first voltage regulator (VR) circuit disposed on a first side of a first substrate; a first magnetically enhanced inductor disposed in the first substrate and having a first end coupled to a power rail of the first VR circuit, wherein the first inductor further comprises: a first through substrate via (TSV) extending through the first substrate; and a first magnetic material disposed over a surface of the first substrate; and a first load circuit disposed on a first side of a second substrate stacked upon the first substrate, wherein the first load circuit is coupled to a second end of the first inductor to receive power from the power rail of the first VR circuit.
10. The device of claim 9 , wherein the first TSV is a magnetic TSV (MTSV) with magnetic material forming a liner disposed on sidewalls of the first TSV and a fill metal disposed within the magnetic material liner with an intervening dielectric liner there between;
wherein the power rail of the first VR circuit electrically couples to a first end of the MTSV;
wherein one or more decoupling capacitor is coupled to a second end of the MTSV through a redistribution metallization layer disposed on a second side of the substrate, opposite the first side; and
wherein the load circuit is coupled to the one or more decoupling capacitors.
11. The device of claim 10 , further comprising a TSV lacking a magnetic liner and electrically coupling the load circuit to a ground rail of the first VR circuit.
12. The device of claim 10 , wherein the first VR circuit comprises a switching supply circuit with one or more power switches communicatively coupled to a switch controller.
13. The device of claim 10 , further comprising:
a second VR circuit disposed on the first side of a first substrate;
a second magnetically enhanced inductor disposed on the first substrate and having a first end coupled to a power rail of the second VR circuit, wherein the second inductor further comprises:
a second TSV extending through the first substrate; and
a magnetic material disposed over a surface of the second substrate; and
a second load circuit disposed on the first side of the second substrate, or disposed on a first side of a third substrate stacked upon the second substrate, wherein the second load circuit is coupled to a second end of the second inductor through one or more decoupling capacitors to receive power from the power rail of the second VR circuit.
14. The device of claim 9 , wherein the magnetic material is disposed on a second side of the first substrate, wherein the first TSV is one of at least a pair of TSVs connected in series by a redistribution metallization layer disposed over the magnetic material to form a three-dimensional coil wherein;
wherein the power rail of the first VR circuit electrically couples to a first end of the first TSV;
wherein one or more decoupling capacitors is coupled to a second end of the series connected TSVs; and
wherein the load circuit is coupled to the one or more decoupling capacitors.
15. The device of claim 9 , further comprising:
a microprocessor;
a wireless communication circuit; and
an antenna coupled to the wireless communication circuit.
16. A microelectronic device, comprising:
an integrated circuit (IC) disposed on a substrate;
a magnetically enhanced inductor disposed in the substrate and electrically coupled to the IC, wherein the inductor further comprises:
a through substrate via (TSV) extending through the substrate; and
a magnetic material disposed over a surface of the substrate, adjacent to a conductive length of the inductor, wherein the TSV is a magnetic TSV (MTSV) with the magnetic material forming a liner on sidewalls of the TSV with a conductive fill metal disposed within the magnetic liner and with an intervening dielectric liner there between.
17. The device of claim 16 , wherein a length of a single MTSV defines a total conductive length of the inductor extending adjacent the magnetic material to form an inductor without needing to form turns along the conductive length.
18. The device of claim 16 , wherein the fill metal has a diameter between 5 and 20 μm, and the magnetic material liner has a thickness between 0.5 and 1.5 μm.
19. The device of claim 16 , wherein the IC further comprises:
a power supply circuit electrically coupled to a first end of the inductor; and
a load circuit electrically coupled to a second end of the inductor to be powered by the power supply circuit.
20. A microelectronic device, comprising:
an integrated circuit (IC) disposed on a frontside of a substrate;
a magnetically enhanced inductor disposed in the substrate and electrically coupled to the IC, wherein the inductor further comprises:
a through substrate via (TSV) extending through the substrate; and
a magnetic material disposed over a surface of a backside of the substrate, adjacent to a conductive length of the inductor, wherein the TSV is one of at least a pair of TSVs coupled in series by a first interconnect metallization disposed over the magnetic material to form a three-dimensional coil, and wherein the first interconnect metallization comprises a redistribution metallization layer.
21. The device of claim 20 , wherein the substrate has a thickness less than 100 μm, and wherein the magnetic material has a thickness no greater than 10 μm.
22. The device of claim 21 , wherein the magnetic material comprises a stack having a plurality of magnetic material layers, wherein adjacent magnetic material layers within the stack are spaced apart by an intervening dielectric layer.
23. The device of claim 20 , wherein the IC further comprises:
a power supply circuit electrically coupled to a first end of the inductor; and a load circuit electrically coupled to a second end of the inductor to be powered by the power supply circuit.
24. A microelectronic device, comprising:
an integrated circuit (IC) disposed on a substrate, the IC comprising a power supply circuit and a load circuit; and
a magnetically enhanced inductor disposed in the substrate and electrically coupled to the IC, wherein the power supply circuit of the IC is electrically coupled to a first end of the inductor, and the load circuit of the IC is electrically coupled to a second end of the inductor to be powered by the power supply circuit, and wherein the inductor comprises:
a through substrate via (TSV) extending through the substrate; and
a magnetic material disposed over a surface of the substrate,
adjacent to a conductive length of the inductor.