Method for producing organic electronic devices with bank structures, bank structures and electronic devices produced therewith

1. A process for preparing an electronic device, wherein a layer is selectively swelled with a swelling solvent, thereby forming bank structures, which define a well.

2. A process according to claim 1 , said process comprising the following steps:

a) depositing a material comprising a polycycloolefinic polymer on a substrate to form a layer; and

b) selectively swelling said layer with a swelling solvent, thereby forming bank structures, which define a well.

3. A process according to claim 2 , wherein the polycycloolefinic polymer is a norbornene-type polymer.

4. A process according to claim 2 , wherein the polycycloolefinic polymer comprises two or more distinct types of repeating units.

5. A process according to claim 2 , wherein the polycycloolefinic polymer comprises a repeating unit comprising a pendant crosslinkable group.

6. A process according to claim 2 , wherein the polycycloolefinic polymer comprises a repeating unit, which comprises a substituted or unsubstituted maleimide portion, an epoxide portion, a vinyl portion, an acetylene portion, an indenyl portion, a cinnamate portion or a coumarin portion.

7. A process according to claim 2 , wherein the polycycloolefinic polymer comprises a repeating unit derived from

8. A process according to claim 1 , wherein the electronic device is an Organic Field Effect Transistor, Organic Thin Film Transistor, Organic Light Emitting Diode, or Organic Photovoltaic device.

9. A process according to claim 1 , wherein the swelling solvent is of formula (R x —O—R y ), (R x —C(═O)H), (R x —OH), (R x —C(═O)—R y ), (R x —C(═O)OH), (R x —C(═O)O—R y ), (HO—(CR x R y —) s COOH), or (HO—(CR x R y —) s COOR z ), wherein R z , R x and R y are independently from one another hydrogen or an alkyl group having from 1 to 10 carbon atoms, provided that either R x or R y is different from hydrogen, and wherein an alkyl group may be linear or branched, and in which alkyl group a hydrogen is optionally replaced by —OH.

10. A process according to claim 9 , wherein R z is methyl, ethyl, propyl or butyl.

11. A process for preparing an electronic device, wherein a layer is selectively swelled with a swelling solvent, thereby forming bank structures, which define a well,

wherein one of the following conditions have been met:

condition 1:

wherein the process comprises the following steps:

a′) depositing a material comprising a polycycloolefinic polymer on a substrate to form a layer;

b′) exposing a part of the surface of said layer to actinic radiation; and

c′) selectively swelling said layer with a swelling solvent, thereby forming bank structures, which define a well;

condition 2:

wherein the process comprises the following steps:

I-a) providing a substrate ( 1 );

I-b) forming a gate electrode ( 2 ) on said substrate ( 1 );

I-c) depositing a dielectric material comprising a polycycloolefinic polymer on said gate electrode ( 2 ) and said substrate ( 1 ) to form a dielectric layer ( 3 );

I-d) forming source and drain electrodes ( 5 ) on said dielectric layer ( 3 ), such that said source and drain electrodes ( 5 ) are spaced apart with a channel region ( 6 ) located between said source and drain electrodes ( 5 );

I-e) exposing a part of the surface of said dielectric layer ( 3 ) to actinic radiation such that the exposed part extends at least over the channel region ( 6 );

I-f) subsequently swelling said dielectric layer ( 3 ) with a swelling solvent, thereby forming bank structures ( 8 a , 8 b ), which define a well that extends at least over the channel region; and

I-g) depositing a layer of semiconductor material ( 7 ) in said well defined by said bank structures ( 8 a , 8 b );

condition 3:

wherein the process comprises the following steps:

II-a) providing a substrate ( 1 );

II-b) forming a gate electrode ( 2 ) on said substrate ( 1 );

II-c) depositing a dielectric material comprising a polycycloolefinic polymer on said gate electrode ( 2 ) and said substrate ( 1 ) to form a dielectric layer ( 3 );

II-d) exposing a part of the surface of said dielectric layer ( 3 ) to actinic radiation;

II-e) subsequently swelling said dielectric layer ( 3 ) with a swelling solvent, thereby forming bank structures ( 8 a , 8 b ), which define a well;

II-f) forming source and drain electrodes ( 5 ) in the well on said dielectric layer ( 3 ), such that source and drain electrodes ( 5 ) are spaced apart with a channel region ( 6 ) located between said source and drain electrodes ( 5 );

II-g) depositing a layer of semiconductor material ( 7 ) in said well defined by said bank structures ( 8 a , 8 b );

condition 4:

wherein the process comprises the following steps:

III-a) providing a substrate ( 1 ′);

III-b) depositing a dielectric material comprising a polycycloolefinic polymer on said substrate ( 1 ′) to form a planarization layer ( 4 ′);

III-c) forming source and drain electrodes ( 5 ′) on said planarization layer ( 4 ′) such that said source and drain electrodes ( 5 ′) are spaced apart with a channel region ( 6 ′) located between said source and drain electrodes ( 5 ′);

III-d) exposing a part of the surface of said planarization layer ( 4 ′) to actinic radiation such that the exposed part extends at least over the channel region ( 6 ′);

III-e) subsequently swelling said planarization layer ( 4 ′) in a swelling solvent, thereby forming bank structures ( 8 a ′, 8 b ′), which define a well that extends at least over the channel region ( 6 ′);

III-f) depositing a layer of semiconductor material ( 7 ′) in the well defined by said bank structures ( 8 a ′, 8 b ′);

III-g) subsequently depositing a further dielectric material to form a gate insulator layer ( 10 ′); and

III-h) forming a gate electrode ( 2 ′) on said gate insulator layer ( 10 ′);

condition 5:

wherein the process comprises the following steps:

IV-a) providing a substrate ( 1 ′);

IV-b) depositing a dielectric material comprising a polycycloolefinic polymer on said substrate ( 1 ′) to form a planarization layer ( 4 ′);

IV-c) exposing a part of the surface of said planarization layer ( 4 ′) to actinic radiation;

IV-d) subsequently swelling said planarization layer ( 4 ′) in a swelling solvent, thereby forming bank structures ( 8 a ′, 8 b ′), which define a well;

IV-e) forming source and drain electrodes ( 5 ′) on said planarization layer ( 4 ′) such that said source and drain electrodes are spaced apart with a channel region ( 6 ′) located between said source and drain electrodes ( 5 ′);

IV-f) depositing a layer of semiconductor material ( 7 ′) in the well defined by said bank structures ( 8 a ′, 8 b ′);

IV-g) subsequently depositing a further dielectric material to form a gate insulator material ( 10 ′); and

IV-h) forming a gate electrode ( 2 ′) on said gate insulator layer ( 10 ′);

condition 6:

wherein, in the process according to condition 2, 3, 4 or 5, the exposed part and the well extend at least over the channel region and at least part of either source or drain electrode or both, source and drain electrode;

condition 7:

wherein the swelling solvent is an organic compound comprising a chemical group selected from the group consisting of —O—, —OH, —C(═O)—, —C(═O)O— and —COOH;

condition 8:

wherein the swelling solvent is an organic compound comprising the chemical groups —OH and —C(═O)O—;

condition 9:

wherein the swelling solvent is of formula HO—(CR x R y —) s COOR z , wherein R z , R x and R y are independently from one another hydrogen or an alkyl group having from 1 to 10 carbon atoms and s is 1, 2 or 3;

condition 10:

wherein the swelling solvent is ethyl lactate (H 5 C 2 —O—C(═O)—C(OH)—CH 3 );

condition 11:

wherein the electronic device is a top gate Organic Field Effect Transistor or a bottom gate Organic Field Effect Transistor.

12. A process according to claim 11 , said process comprising the following steps:

a′) depositing a material comprising a polycycloolefinic polymer on a substrate to form a layer;

b′) exposing a part of the surface of said layer to actinic radiation; and

c′) selectively swelling said layer with a swelling solvent, thereby forming bank structures, which define a well.

13. A process according to claim 11 , said process comprising the following steps:

I-a) providing a substrate ( 1 );

I-b) forming a gate electrode ( 2 ) on said substrate ( 1 );

I-c) depositing a dielectric material comprising a polycycloolefinic polymer on said gate electrode ( 2 ) and said substrate ( 1 ) to form a dielectric layer ( 3 );

I-d) forming source and drain electrodes ( 5 ) on said dielectric layer ( 3 ), such that said source and drain electrodes ( 5 ) are spaced apart with a channel region ( 6 ) located between said source and drain electrodes ( 5 );

I-e) exposing a part of the surface of said dielectric layer ( 3 ) to actinic radiation such that the exposed part extends at least over the channel region ( 6 );

I-f) subsequently swelling said dielectric layer ( 3 ) with a swelling solvent, thereby forming bank structures ( 8 a , 8 b ), which define a well that extends at least over the channel region; and

I-g) depositing a layer of semiconductor material ( 7 ) in said well defined by said bank structures ( 8 a , 8 b ).

14. A process according to claim 13 , wherein the exposed part and the well extend at least over the channel region and at least part of either source or drain electrode or both, source and drain electrode.

15. A process according to claim 11 , said process comprising the following steps:

II-a) providing a substrate ( 1 );

II-b) forming a gate electrode ( 2 ) on said substrate ( 1 );

II-c) depositing a dielectric material comprising a polycycloolefinic polymer on said gate electrode ( 2 ) and said substrate ( 1 ) to form a dielectric layer ( 3 );

II-d) exposing a part of the surface of said dielectric layer ( 3 ) to actinic radiation;

II-e) subsequently swelling said dielectric layer ( 3 ) with a swelling solvent, thereby forming bank structures ( 8 a , 8 b ), which define a well;

II-f) forming source and drain electrodes ( 5 ) in the well on said dielectric layer ( 3 ), such that source and drain electrodes ( 5 ) are spaced apart with a channel region ( 6 ) located between said source and drain electrodes ( 5 );

II-g) depositing a layer of semiconductor material ( 7 ) in said well defined by said bank structures ( 8 a , 8 b ).

16. A process according to claim 15 , wherein the exposed part and the well extend at least over the channel region and at least part of either source or drain electrode or both, source and drain electrode.

17. A process according to claim 11 , said process comprising the following steps

III-a) providing a substrate ( 1 ′);

III-b) depositing a dielectric material comprising a polycycloolefinic polymer on said substrate ( 1 ′) to form a planarization layer ( 4 ′);

III-c) forming source and drain electrodes ( 5 ′) on said planarization layer ( 4 ′) such that said source and drain electrodes ( 5 ′) are spaced apart with a channel region ( 6 ′) located between said source and drain electrodes ( 5 ′);

III-d) exposing a part of the surface of said planarization layer ( 4 ′) to actinic radiation such that the exposed part extends at least over the channel region ( 6 ′);

III-e) subsequently swelling said planarization layer ( 4 ′) in a swelling solvent, thereby forming bank structures ( 8 a ′, 8 b ′), which define a well that extends at least over the channel region ( 6 ′);

III-f) depositing a layer of semiconductor material ( 7 ′) in the well defined by said bank structures ( 8 a ′, 8 b ′);

III-g) subsequently depositing a further dielectric material to form a gate insulator layer ( 10 ′); and

III-h) forming a gate electrode ( 2 ′) on said gate insulator layer ( 10 ′).

18. A process according to claim 11 , said process comprising the following steps:

IV-a) providing a substrate ( 1 ′);

IV-b) depositing a dielectric material comprising a polycycloolefinic polymer on said substrate ( 1 ′) to form a planarization layer ( 4 ′);

IV-c) exposing a part of the surface of said planarization layer ( 4 ′) to actinic radiation;

IV-d) subsequently swelling said planarization layer ( 4 ′) in a swelling solvent, thereby forming bank structures ( 8 a ′, 8 b ′), which define a well;

IV-e) forming source and drain electrodes ( 5 ′) on said planarization layer ( 4 ′) such that said source and drain electrodes are spaced apart with a channel region ( 6 ′) located between said source and drain electrodes ( 5 ′);

IV-f) depositing a layer of semiconductor material ( 7 ′) in the well defined by said bank structures ( 8 a ′, 8 b ′);

IV-g) subsequently depositing a further dielectric material to form a gate insulator material ( 10 ′); and

IV-h) forming a gate electrode ( 2 ′) on said gate insulator layer ( 10 ′).

19. A process according to claim 11 , wherein the swelling solvent is an organic compound comprising a chemical group selected from the group consisting of —O—, —OH, —C(═O)—, —C(═O)O— and —COOH.

20. A process according to claim 11 , wherein the swelling solvent is an organic compound comprising the chemical groups —OH and —C(═O)O—.

21. A process according to claim 11 , wherein the swelling solvent is of formula HO—(CR x R y —) s COOR z , wherein R z , R x and R y are independently from one another hydrogen or an alkyl group having from 1 to 10 carbon atoms and s is 1, 2 or 3.

22. A process according to claim 21 , wherein R z is methyl, ethyl, propyl or butyl.

23. A process according to claim 11 , wherein the swelling solvent is ethyl lactate (H 5 C 2 —O—C(═O)—C(OH)—CH 3 ).

24. A process according to claim 11 , wherein the electronic device is a top gate Organic Field Effect Transistor or a bottom gate Organic Field Effect Transistor.