IP Library Granted Patent US 9,923,358
Granted Patent B2
US 9,923,358 · App. 14/619,659 · Granted Mar 20, 2018

USB adapter protection

Inventors: Zhibo Tao (San Jose, CA); David Kunst (Cupertino, CA); Won-Seok Kang (Bucheon, KR); Ke Hong (Cupertino, CA)
Assignee: Fairchild Semiconductor Corporation
H02H1/0007H02H3/16
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Quick Facts
Patent No.
US 9,923,358
App. No.
14/619,659
Granted
Mar 20, 2018
Kind
B2
Abstract

This document discusses, among other things, a protection system and method configured to detect a parasitic impedance between first and second pins of a standard connector and to remove a current path between a power source and a supply pin of the standard connector if a low-impedance is detected, in certain examples, without adding a current sense resistance to a return path between a ground pin of the standard connector and the power source.

Claims (49)

1. A protection circuit, comprising:

a first switch configured to provide a current path between a power source and a supply pin of a standard connector in a first state and to remove the current path between the power source and the supply pin of the standard connector in a second state; and

a detection circuit configured to detect a parasitic impedance based on a voltage drop between first and second pins of the standard connector and to control the first switch using the detected voltage, the detection circuit including a second switch in parallel with the first switch.

2. The protection circuit of claim 1 , wherein the detection circuit is configured to compare the voltage drop between the first and second pins of the standard connector to a reference and to control the first switch using the comparison.

3. The protection circuit of claim 1 , wherein the detection circuit is configured to detect the voltage drop between the first and second pins of the standard connector without adding a current sense resistance to a return path between a ground pin of the standard connector and the power source.

4. The protection circuit of claim 1 , wherein the first switch includes:

a first terminal coupled to the power source;

a second terminal coupled to the supply pin of the standard connector; and

a control terminal coupled to the detection circuit,

wherein the first state includes a low-impedance state between the first and second terminals and the second state includes a high-impedance state between the first and second terminals.

5. The protection circuit of claim 4 , wherein the first switch includes a first transistor, wherein the control terminal of the first switch includes a gate of the first transistor, and wherein the detection circuit includes control logic configured to drive the gate of the transistor.

6. The protection circuit of claim 1 , wherein the power source includes a travel adapter including a supply configured to provide power to the standard connector through the first switch and a ground connection configured to provide a return path.

7. The protection circuit of claim 1 , wherein the supply pin of the standard connector includes a voltage bus (VBUS) pin of a universal serial bus (USB) connector.

8. The protection circuit of claim 7 , wherein the first pin includes one of a VBUS pin, a data plus (D+) pin, or a data minus (D−) pin of the USB connector, and the second pin includes a ground (GND) pin of the USB connector.

9. The protection circuit of claim 1 , wherein the second switch has a first terminal, a second terminal, and a control terminal, the first terminal of the second switch being coupled to the power source; and

the detection circuit including:

a resistor having a first terminal coupled to the second terminal of the second switch and a second terminal coupled to the supply pin of the standard connector, the resistor configured to form a voltage divider with the parasitic impedance between the first and second pins of the standard connector,

the detection circuit is configured to compare the voltage on the second terminal of the resistor to a reference and to control the first switch using the comparison.

10. The protection circuit of claim 1 , wherein the detection circuit includes:

a current source configured to provide a current between the first and second pins of the standard connector,

the detection circuit is configured to detect the voltage between the first and second pins of the standard connector in response to the provided current and to control the first switch using the detected voltage.

11. A protection method, comprising:

providing a current path between a power source and a supply pin of a standard connector using a first switch in a first state;

removing the current path between the power source and the supply pin of the standard connector using the first switch in a second state;

detecting a parasitic impedance based on a voltage drop between first and second pins of the standard connector using a detection circuit, the detection circuit including a second switch in parallel with the first switch; and

controlling the switch using the detected voltage.

12. The protection method of claim 11 , including:

comparing the voltage drop between the first and second pins of the standard connector to a reference,

the controlling the first switch includes using the comparison.

13. The protection method of claim 11 , wherein the detecting a voltage drop between the first and second pins of the standard connector includes detecting the voltage drop without adding a current sense resistance to a return path between a ground pin of the standard connector and the power source.

14. The protection method of claim 11 , wherein the power source includes a travel adapter including a supply configured to provide power to the standard connector through the first switch and a ground connection configured to provide a return path.

15. The protection method of claim 11 , wherein the supply pin includes a voltage bus (VBUS) pin of a universal serial bus (USB) connector.

16. The protection method of claim 15 , wherein the detecting the voltage drop between the first and second pins of the standard connector includes detecting a voltage across a parasitic impedance between one of a VBUS pin, a data plus (D+) pin, or a data minus (D−) pin of the USB connector and a ground (GND) pin of the USB connector.

17. The protection method of claim 11 , wherein the detecting a voltage drop between the first and second pins of the standard connector includes:

dividing a voltage between a resistor and the parasitic impedance between the first and second pins of the standard connector while the first switch is in the second state, wherein the resistor is coupled between a second transistor and the supply pin of the standard connector; and

comparing the voltage at the supply pin of the standard connector to a reference,

the controlling the first switch includes using the comparison.

18. The protection method of claim 11 , wherein the detecting a voltage drop between the first and second pins of the standard connector includes:

providing a current across the parasitic impedance between the first and second pins of the standard connector using a current source; and

detecting a voltage across the parasitic impedance between the first and second pins of the standard connector in response to the provided current.

19. A protection system, comprising:

a power source including a supply and a ground connection;

a standard connector including a supply pin and a ground pin;

a first switch configured to provide a current path between the supply of the power source and the supply pin of the standard connector in a first state and to remove the current path between the supply of the power source and the supply pin of the standard connector in a second state; and

a detection circuit configured to detect a parasitic impedance based on a voltage drop between first and second pins of the standard connector and to control the first switch using the detected voltage, the detection circuit including a second switch in parallel with the first switch.

20. The protection system of claim 19 , wherein the detection circuit is configured to detect the voltage drop between the first and second pins of the standard connector without adding a current sense resistance to a return path between the ground pin of the standard connector and the ground connection of the power source,

the supply pin of the standard connector includes a voltage bus (VBUS) pin of a universal serial bus (USB) connector,

the first pin includes one of a VBUS pin, a data plus (D+) pin, or a data minus (D−) pin of the USB connector, and the second pin includes a ground (GND) pin of the USB connector.

21. The protection circuit of claim 1 , wherein the detection circuit further includes a resistor coupled in series with the second switch and in parallel with the first switch, the resistor configured to form a voltage divider with the parasitic impedance between the first and second pins, the detection circuit is configured to compare the voltage at the resistor to a reference and to control the first switch using the comparison.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 040075, FRAME 0644 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0536 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2017
From: TAO, ZHIBO; KUNST, DAVID; KANG, WON-SEOK; HONG, KE
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 042163/0038 →
PATENT SECURITY AGREEMENT Recorded Sep 19, 2016
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 040075/0644 →
Continuity (2)
Provisional Application 61938530 · Feb 11, 2014
Related Publication 20150229119A1 · Aug 13, 2015