Methods and systems for performing a binary translation

1. A method for performing binary translation, comprising:

identifying a hot code trace in a source binary application being interpreted by an interpreter module, wherein the identifying is based, at least in part, on determining a frequency of execution of the hot code trace;

performing a translation of one or more source instructions of the hot code trace to target instructions;

invoking, by a translator module loaded in system memory, an optimizer module based on identifying a condition code block in the hot code trace, wherein the condition code block includes a plurality of condition bits, and wherein the optimizer module is loaded in system memory and executed by a processor to transform the condition code block into a transformed code by:

decoding the condition bits on a conditions-specifying instruction of the condition code block;

statically advancing a condition state and resolving the condition bits on each instruction following the conditions-specifying instruction to form a pre-resolved condition set;

removing the conditions-specifying instruction; and

encoding the one or more source instructions of the hot code trace with the pre-resolved condition set.

2. The method of claim 1 , wherein the translator module, based on identifying the hot code trace, performs the translation of the one or more source instructions of the hot code trace, wherein the optimizer module is invoked during the translation.

3. The method of claim 1 , further comprising:

receiving, by the translator module, an instruction to be translated, wherein the instruction calls for a parallel multiply addition function for a number of source vectors; and

generating translated code to perform:

executing the parallel multiply addition function for the number of source vectors; and

determining whether there is an overflow.

4. The method of claim 3 , further comprising:

responsive to determining an overflow, setting an overflow flag to indicate there is overflow.

5. The method of claim 1 , further comprising:

receiving, by the translator module, an instruction to be translated, wherein the instruction calls for a parallel multiply subtraction function for a plurality of source vectors, wherein each vector of the plurality of source vectors has a low element and a high element; and

generating translated code to perform:

performing a bitwise-not operation on a low element of a second source vector;

executing the parallel multiply addition function for the plurality of source vectors to form a result;

adding a low element of the first source vector to the result;

determining whether there is an overflow; and

responsive to determining an overflow, setting the result to a constant value.

6. The method of claim 5 , further comprising:

responsive to not determining an overflow, determining whether the high elements were subtracted from the low elements; and

responsive to the high elements being subtracted from the low elements, performing a bitwise-not operation on the result.

7. The method of claim 1 , further comprising:

receiving, by the translator module, an instruction to be translated, wherein the instruction calls for a partial long multiply function for a plurality of source vectors, and wherein the partial long multiply function has a first operand; and

generating translated code to perform:

splitting the first operand of the function into an upper half and a lower half;

multiplying each half of the first operand with a second operand to form an upper half product and a lower half product; and

adding the upper half product to the lower half product.

8. The method of claim 7 , wherein the splitting the first operand of the function comprises:

performing a zero-extend operation on the lower half; and

performing an arithmetic shift right operation on the upper half.

9. The method of claim 7 , further comprising:

performing an arithmetic shift right operation on the lower half product.

10. At least one non-transitory computer-readable medium comprising one or more instructions that when executed by a processor:

identify a hot code trace in a source binary application being interpreted, wherein the identifying is based, at least in part, on determining a frequency of execution of the hot code trace;

perform a translation of one or more source instructions of the hot code trace to target instructions;

identify a condition code block in the hot code trace, wherein the condition code block includes a plurality of condition bits; and

transform the condition code block into a transformed code, wherein the transforming includes:

decoding the condition bits on a conditions-specifying instruction of the condition code block;

statically advancing a condition state and resolving the condition bits on each instruction following the conditions-specifying instruction to form a pre-resolved condition set;

removing the conditions-specifying instruction; and

encoding the one or more source instructions of the hot code trace with the pre-resolved condition set.

11. The at least one non-transitory computer-readable medium of claim 10 , further comprising one or more instructions that when executed by the processor:

perform the translation, based on identifying the hot code trace, wherein the condition code block is transformed into the transformed code during the translation.

12. The at least one non-transitory computer-readable medium of claim 10 , further comprising one or more instructions that when executed by the processor:

receive an instruction to be translated, wherein the instruction calls for a parallel multiply addition function for a number of source vectors; and

generate translated code to:

execute the parallel multiply addition function for the number of source vectors; and

determine whether there is an overflow.

13. The at least one non-transitory computer-readable medium of claim 12 , further comprising one or more instructions that when executed by the processor:

responsive to determining an overflow, set an overflow flag to indicate there is overflow.

14. The at least one non-transitory computer-readable medium of claim 10 , further comprising one or more instructions that when executed by the processor:

receive an instruction to be translated, wherein the instruction calls for a parallel multiply subtraction function for a plurality of source vectors, wherein each vector of the plurality of source vectors has a low element and a high element; and

generate translated code to:

perform a bitwise-not operation on a low element of a second source vector;

execute the parallel multiply addition function for the plurality of source vectors to form a result;

add a low element of the first source vector to the result;

determine whether there is an overflow; and

responsive to determining an overflow, set the result to a constant value.

15. The at least one non-transitory computer-readable medium of claim 14 , further comprising one or more instructions that when executed by the processor:

responsive to not determining an overflow, determine whether the high elements were subtracted from the low elements; and

responsive to the high elements being subtracted from the low elements, perform a bitwise-not operation on the result.

16. The at least one non-transitory computer-readable medium of claim 10 , further comprising one or more instructions that when executed by the processor:

receive an instruction to be translated, wherein the instruction calls for a partial long multiply function for a plurality of source vectors, and wherein the partial long multiply function has a first operand; and

generate translated code to:

split the first operand of the function into an upper half and a lower half;

multiply each half of the first operand with a second operand to form an upper half product and a lower half product; and

add the upper half product to the lower half product.

17. The at least one non-transitory computer-readable medium of claim 16 , wherein the splitting the first operand of the function comprises one or more instructions that when executed by the processor:

perform a zero-extend operation on the lower half; and

perform an arithmetic shift right operation on the upper half.

18. The at least one non-transitory computer-readable medium of claim 16 , further comprising one or more instructions that when executed by the processor:

perform an arithmetic shift right operation on the lower half product.