3-5 device with doped regions and method of fabricating

1. A semiconductor device, comprising:

a carrier transit layer including a first region and second and third regions having a density of a donor impurity element higher than that of the first region;

an In X Al Y Ga (1-X-Y) N (0<X<1, 0<Y<1, 0<X+Y≤1) carrier supply layer provided over the carrier transit layer and a whole of the carrier supply layer having a density of a donor impurity element lower than that of the second and third regions;

a source electrode provided over the second region;

a drain electrode provided over the third region; and

a gate electrode provided over the carrier supply layer between the source electrode and the drain electrode.

2. The semiconductor device according to claim 1 , further comprising:

a spacer layer provided between the carrier transit layer and the carrier supply layer and includes a first region and second and third regions having a density of a donor impurity element higher than that of the first region; wherein

the source electrode is provided over the second region of the carrier transit layer and the second region of the spacer layer; and

the drain electrode is provided over the third region of the carrier transit layer and the third region of the spacer layer.

3. The semiconductor device according to claim 1 , further comprising a spacer layer provided between the carrier transit layer and the carrier supply layer and having a density of a donor impurity element lower than that of the second and third regions.

4. The semiconductor device according to claim 1 , wherein the carrier supply layer includes a first region provided over the first region of the carrier transit layer, a second region provided between the second region of the carrier transit layer and the source electrode and a third region provided between the third region of the carrier transit layer and the drain electrode; wherein

the second region and the third region of the carrier supply layer have a thickness smaller than that of the first region of the carrier supply layer.

5. The semiconductor device according to claim 4 , wherein the thickness of the second region and the third region of the carrier supply layer is 3 nm or less.

6. The semiconductor device according to claim 1 , wherein the carrier supply layer is provided over the first region of the carrier transit layer.

7. The semiconductor device according to claim 1 , wherein the carrier supply layer includes a first region provided over the first region of the carrier transit layer, a second region provided between the second region of the carrier transit layer and the source electrode, and a third region provided between the third region of the carrier transit layer and the drain electrode; and

the first, second and third regions of the carrier supply layer have a thickness equal to or smaller than 3 nm.

8. The semiconductor device according to claim 1 , wherein the donor impurity element is one of Si, O, S, Ge, Te and Se.

9. A power supply apparatus, comprising:

a transistor; wherein

the transistor includes:

a carrier transit layer including a first region and second and third regions having a density of a donor impurity element higher than that of the first region;

an In X Al Y Ga (1-X-Y) N (0<X<1, 0<Y<1, 0<X+Y≤1) carrier supply layer provided over the carrier transit layer and a whole of the carrier supply layer having a density of a donor impurity element lower than that of the second and third regions;

a source electrode provided over the second region;

a drain electrode provided over the third region; and

a gate electrode provided over the carrier supply layer between the source electrode and the drain electrode.

10. A high-frequency amplifier, comprising:

an amplifier configured to amplify an input signal; wherein

the amplifier includes a transistor; and

the transistor includes:

a carrier transit layer including a first region and second and third regions having a density of a donor impurity element higher than that of the first region;

an In X Al Y Ga (1-X-Y) N (0<X<1, 0<Y<1, 0<X+Y≤1) carrier supply layer provided over the carrier transit layer and a whole of the carrier supply layer having a density of a donor impurity element lower than that of the second and third regions;

a source electrode provided over the second region;

a drain electrode provided over the third region; and

a gate electrode provided over the carrier supply layer between the source electrode and the drain electrode.

11. A fabrication method for a semiconductor device, comprising:

forming a carrier transit layer including a first region and second and third regions having a density of a donor impurity element higher than that of the first region;

forming, over the carrier transit layer, an In X Al Y Ga (1-X-Y) N (0<X<1, 0<Y<1, 0<X+Y≤1) carrier supply layer, a whole of the carrier supply layer having a density of a donor impurity element lower than that of the second and third regions;

forming a source electrode over the second region and forming a drain electrode over the third region; and

forming a gate electrode over the carrier supply layer between the source electrode and the drain electrode.

12. The fabrication method for a semiconductor device according to claim 11 , wherein the forming a carrier transit layer includes performing ion implantation of the donor impurity element into the second and third regions and performing annealing for activating ions of the donor impurity element after ion implantation.

13. The fabrication method for a semiconductor device according to claim 11 , further comprising, before the forming a carrier supply layer, forming, over the carrier transit layer, a spacer layer including a first region and second and third regions having a density of a donor impurity element higher than that of the first region; and

the forming a carrier transit layer and the forming a spacer layer include performing ion implantation of the donor impurity element into the second and third regions of the carrier transit layer and the second and third regions of the spacer layer and performing annealing for activating ions of the donor impurity element after ion implantation.

14. The fabrication method for a semiconductor device according to claim 11 , further comprising forming a spacer layer over the carrier transit layer before the forming a carrier supply layer; and

the forming a carrier transit layer and the forming a spacer layer include performing ion implantation of the donor impurity element into the second and third regions of the carrier transit layer and forming a spacer layer at a temperature at which ions of the donor impurity element after ion implantation are capable of being activated.

15. The fabrication method for a semiconductor device according to claim 11 , further comprising, after the forming a carrier supply layer but before the forming a source electrode and a drain electrode, reducing a thickness of a portion of the carrier supply layer provided over the second and third regions of the carrier transit layer with respect to that of the other portion of the carrier supply layer.

16. The fabrication method for a semiconductor device according to claim 11 , further comprising, after the forming a carrier supply layer but before the forming a source electrode and a drain electrode, removing a portion of the carrier supply layer provided over the second and third regions of the carrier transit layer.

17. The fabrication method for a semiconductor device according to claim 11 , wherein, in the forming a carrier supply layer, the carrier supply layer having a thickness of 3 nm or less is formed over the first, second and third regions of the carrier transit layer.