Apparatus for physically unclonable function (PUF) for a memory array
Methods and apparatus for creating a physically unclonable function for SRAM are disclosed. An example method includes after applying a voltage to a memory array: determining a first duration between the applying of the voltage and a first output of a first bit cell, the first output corresponding to a first value stored in the first bit cell, and determining a second duration between the applying of the voltage and a second output of a second bit cell, the second output corresponding to a second value stored in the second bit cell. The example method further includes determining a function based on a comparison of the first duration and the second duration, the function to establish an identification of a circuit that includes the memory array.
1. An apparatus comprising:
a memory array comprising a first bit cell and a second bit cell;
a voltage source to apply a voltage to the memory array;
a timer to:
after the voltage is applied to the memory array:
determine a first duration between the applying of the voltage and a first output of the first bit cell of the memory array, the first output corresponding to a first value stored in the first bit cell; and
determine a second duration between the applying of the voltage and a second output of the second bit cell of the memory array, the second output corresponding to a second value stored in the second bit cell; and
a processor to determine a physically unclonable function based on a comparison of the first duration and the second duration, the physically unclonable function to establish an identification of a circuit that includes the memory array.
2. The apparatus of claim 1 , wherein the processor is structured to generate an identifier based on the physically unclonable function, the identifier to identify the circuit.
3. The apparatus of claim 1 , wherein the memory array is a random access memory array.
4. The apparatus of claim 3 , wherein the random access memory array is a static random access memory (SRAM) array.
5. The apparatus of claim 1 , wherein the voltage is a read voltage that initiates a read operation, the read voltage being on a wordline of the memory array.
6. The apparatus of claim 5 , wherein the voltage source is structured to apply a supply voltage to the memory array and to decrease the supply voltage prior to applying the read voltage.
7. The apparatus of claim 1 , wherein the timer is to determine a third duration between the applying of the voltage and a third output of a third bit cell, the third output corresponding to a third value stored in the third bit cell, the determining of the physically unclonable function being further based on a comparison of the first duration, the second duration, and the third duration.
8. The apparatus of claim 1 , further including a transmitter to transmit the physically unclonable function to a database.
9. An apparatus comprising:
a memory array comprising a bit cell;
a voltage source to apply a voltage to the memory array;
a bit cell determiner to:
after applying a voltage to the memory array:
measure, at a first time, a first output from the bit cell of the memory array; and
measure, at a second time later than the first time, a second output from the bit cell; and
a processor to determine a physically unclonable function based on a difference between the first output and the second output, the physically unclonable function to represent an identification of a circuit that includes the memory array.
10. The apparatus of claim 9 , wherein the processor is structured to generate an identifier based on the physically unclonable function, the identifier to identify the circuit.
11. The apparatus of claim 9 , wherein the memory array is a random access memory array.
12. The apparatus of claim 9 , wherein the voltage is a read voltage, the read voltage initiates a read operation, and the read voltage is on a wordline of the memory array.
13. The apparatus of claim 12 , wherein the voltage source is structured to apply a supply voltage to the memory array and is to decrease the supply voltage prior to applying the read voltage.
14. The apparatus of claim 9 , wherein the bit cell determiner is structured to measure, at a third time later than the second time, a third output from the bit cell, the determining of the physically unclonable function being further based on a comparison of the first output, the second output, and the third output.
15. The apparatus of claim 9 , wherein the bit cell determiner is structured to:
measure, at the first time, a third output from a second bit cell; and
measure, at the second time, a fifth output from the second bit cell, the determining of the physically unclonable function being further based on a comparison of the first output, the second output, the third output, the fourth output and the fifth output.
16. The apparatus of claim 9 , further including a transmitter to transmit the physically unclonable function to a database.
17. The apparatus of claim 11 , wherein the random access memory array is a static random access memory (SRAM) array.