Thin film transistor substrate, display panel including the same, and method of manufacturing the same

1. An electronic display panel comprising:

a plastic substrate;

a bottom shield metal (BSM) on the plastic substrate;

a thin-film transistor (TFT) on the BSM, the TFT and the BSM at least partially overlapping each other; and

an active buffer layer between the TFT and the BSM,

wherein the BSM is connected to one of a gate electrode, a source electrode, and a drain electrode of the TFT,

wherein an active layer of the TFT includes a plurality of doping areas and a channel between the doping areas that has lower doping-concentration than the doping areas,

wherein a length of the channel is greater than a length of the BSM, and

wherein the length of the channel covers an entire length of the BSM.

2. The electronic display panel of claim 1 , wherein the TFT is one of a plurality of switching TFTs of the plastic substrate, and

wherein a length of the BSM is less than a length of the gate electrode of the TFT.

3. The electronic display panel of claim 1 , wherein each of the doping areas includes a plurality of low-concentration doped portions and a plurality of high-concentration doped portions further away from the channel than the low-concentration doped portions in the respective doping area,

wherein the BSM overlaps an entire portion of at least one of the low-concentration doped portions, and

wherein the BSM partially overlaps at least one of the high-concentration doped portions.

4. The electronic display panel of claim 1 , wherein the TFT on the BSM is a driving TFT of the plastic substrate, and

wherein a length of the BSM is greater than or equal to a length of the gate electrode of the TFT.

5. The electronic display panel of claim 1 , wherein the TFT and the BSM asymmetrically overlap each other, and

wherein the TFT is one of a plurality of switching TFTs of the plastic substrate.

6. The electronic display panel of claim 1 , wherein the TFT is a dual gate TFT branching the gate electrode thereof into a first gate electrode terminal and a second gate electrode terminal, the TFT including the channel having a first channel corresponding to the first gate electrode terminal and a second channel corresponding to the second gate electrode terminal, and

wherein the BSM is under at least one of the first channel and the second channel.

7. The electronic display panel of claim 6 , wherein the BSM overlaps either the first channel or the second channel,

wherein a length of one of the first channel and the second channel is less than or equal to a length of the BSM, and

wherein the length of the BSM covers an entire length of the one of the first channel and the second channel, and

wherein the TFT is a driving TFT of the plastic substrate.

8. The electronic display panel of claim 7 , wherein the BSM is closer to the drain electrode than the source electrode of the TFT.

9. The electronic display panel of claim 6 , wherein the BSM is closer to one that is supplied a higher voltage among the source electrode and the drain electrode of the TFT.

10. The electronic display panel of claim 1 , wherein the TFT on the BSM is in a pixel circuit and the BSM extends under one of a plurality of component interconnecting nodes in the pixel circuit, and

wherein the component interconnecting node is floated during a period of operation of the pixel circuit.

11. The electronic display panel of clam 10 , wherein the period is an emission period of an organic light-emitting diode (OLED).

12. An electronic display panel comprising:

a plastic substrate;

a bottom shield metal (BSM) on the plastic substrate, the BSM located to minimize formation of a back channel in a pixel circuit by trapped charges of the plastic substrate;

an active buffer layer on the BSM; and

the pixel circuit in a pixel area defined by a gate line and a data line on the plastic substrate, the pixel circuit on the active buffer layer including a plurality of TFTs and a plurality of component interconnecting nodes,

wherein the BSM overlaps one of the TFTs of the pixel circuit and is connected to one of a gate electrode, a source electrode, and a drain electrode of the one of the TFTs overlapping the BSM,

wherein an active layer of the TFT includes a plurality of doping areas and a channel between the doping areas that has lower doping-concentration than the doping areas,

wherein a length of the channel is less than or equal to a length of the BSM, and

wherein the length of the BSM covers an entire length of the channel.

13. The electronic display panel of claim 12 , wherein the BSM overlaps one of the component interconnecting nodes floated at during a period of operation of the pixel circuit and is connected to one of a plurality of power sources of the pixel circuit.

14. The electronic display panel of claim 12 , wherein the BSM extends under one of the TFTs in the pixel circuit.