IP Library Granted Patent US 9,934,981
Granted Patent B2
US 9,934,981 · App. 14/230,649 · Granted Apr 3, 2018

Techniques for processing substrates using directional reactive ion etching

Inventors: Steven R. Sherman (Newton, MA); Simon Ruffell (South Hamilton, MA); John Hautala (Beverly, MA); Adam Brand (Palo Alto, CA)
Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
H01L21/3065H01J37/32357H01J37/32422H01L29/66803
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Quick Facts
Patent No.
US 9,934,981
App. No.
14/230,649
Granted
Apr 3, 2018
Kind
B2
Abstract

A method of treating a substrate includes directing ions to the substrate along at least one non-zero angle with respect to a perpendicular to a substrate surface in a presence of a reactive ambient containing a reactive species where the substrate includes a surface feature. At least one surface of the surface feature is etched using the ions in combination with the reactive ambient at a first etch rate that is greater than a second etch rate when the ions are directed to the substrate without the reactive ambient and greater than a third etch rate when the reactive ambient is provided to the substrate without the ions.

Claims (17)

1. A method of treating a substrate, comprising:

providing a top feature on a side of the substrate;

providing a first material over the top feature;

providing a reactive gas ambient in contact with the side of the substrate, an outer surface of the side of the substrate comprising the first material defining a first outer surface in first regions, and a second material disposed under the first material in the first regions, the second material defining a second outer surface in second regions of the side of the substrate;

directing a first dose of ions to the substrate in a presence of the reactive gas ambient at an incidence angle the incidence angle forming a non-zero angle with respect to a perpendicular to the side of the substrate, the ions configured to etch an angled feature into the second material along a direction parallel to the incidence angle of the ions, wherein the angled feature contacts a buried feature, and wherein the buried feature is disposed under the top feature.

2. The method of claim 1 , the first material comprising a mask material and the second material comprising an interlevel dielectric.

3. The method of claim 2 wherein the buried feature is disposed at a bottom surface of the interlevel dielectric.

4. The method of claim 2 , wherein the angled feature is a contact via, wherein the contact via is arranged to expose the buried feature.

5. The method of claim 1 , wherein the angled feature is an angled via or an angled trench.

6. The method of claim 1 , wherein the buried feature is a buried conductor.

7. A method of treating a substrate, comprising:

directing ions to the substrate along at least one non-zero angle with respect to a perpendicular to a substrate surface in a presence of a reactive ambient containing a reactive species, the substrate including a surface feature; and

etching, using the ions in combination with the reactive ambient, at least one surface of the surface feature, wherein the surface feature comprises:

three or more layers, wherein a top layer comprises a first material having a top surface, a second layer adjacent the top layer comprises a second material, and a third layer adjacent the second layer comprises a material different than the second material;

a pair of opposed sidewalls oriented along a first direction; and

a pair of covered portions comprising a fourth material disposed on the opposing sidewalls and top surface and defining an exposed portion of the patterned feature therebetween wherein the directing ions comprises directing ions to at least one sidewall of the pair of opposed sidewalls at the non-zero angle, wherein the directing the ions comprises etching the second layer at a first etch rate and etching the top layer and third layer at etch rates that are less than the first etch rate, wherein a tunnel is formed in the second layer.

8. The method of claim 7 wherein the top layer forms a channel of a gate-all-around transistor after the etching.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 8, 2014
From: SHERMAN, STEVEN R.; RUFFELL, SIMON; HAUTALA, JOHN; BRAND, ADAM
To: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
Reel/Frame 032628/0743 →
Continuity (3)
Provisional Application 61882926 · Sep 26, 2013
Provisional Application 61896042 · Oct 26, 2013
Related Publication 20150083581A1 · Mar 26, 2015