IP Library › Granted Patent US 9,935,053
Granted Patent B2
US 9,935,053 · App. 15/409,766 · Granted Apr 3, 2018

Electronic component integrated substrate

Inventors: Satoshi Shiraki (Nagano, JP); Koichi Tanaka (Nagano, JP)
Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
H01L23/5389H01L21/486H01L21/4853H01L21/563H01L21/565H01L23/3142H01L23/5384H01L23/5385H01L23/5386H05K1/144H05K3/3436H05K2201/042H05K2201/10674H05K2201/10977
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Quick Facts
Patent No.
US 9,935,053
App. No.
15/409,766
Granted
Apr 3, 2018
Kind
B2
Abstract

An electronic component integrated substrate includes a first substrate including a first pad, a first solder resist layer provided with a first open portion that selectively exposes the first pad, and a connection pad formed on the first solder resist layer, and electrically connected to the first pad; a second substrate, stacked on the first substrate, including a second pad, and a second solder resist layer formed on the second pad and provided with a second open portion that selectively exposes the second pad; an electronic component mounted on the first substrate and sandwiched between the first substrate and the second substrate; and a substrate connection member that electrically connects the connection pad and the second pad with each other, the diameter of the connection pad being larger than each of the diameter of the first pad and the diameter of the second open portion.

Claims (26)

1. An electronic component integrated substrate comprising:

a first substrate including

a first pad,

a first solder resist layer that is formed as an outermost insulating layer of the first substrate on the first pad and provided with a first open portion that selectively exposes the first pad, and

a connection pad formed on the first solder resist layer, and electrically connected to the first pad via a conductive material provided in the first open portion;

a second substrate including

a second pad, and

a second solder resist layer formed on the second pad and provided with a second open portion that selectively exposes the second pad,

the second substrate being stacked on the first substrate while facing the second pad toward the connection pad;

an electronic component mounted on the first substrate and sandwiched between the first substrate and the second substrate; and

a substrate connection member that electrically connects the connection pad and the second pad with each other,

the diameter of the connection pad being larger than each of the diameter of the first pad and the diameter of the second open portion.

2. The electronic component integrated substrate according to claim 1 , wherein the diameter of the second open portion is larger than the diameter of the first pad.

3. The electronic component integrated substrate according to claim 1 , further comprising resin that is filled between the first substrate and the second substrate to seal the substrate connection member and the electronic component, the resin covering a side surface of the connection pad.

4. The electronic component integrated substrate according to claim 1 , further comprising:

a plurality of the first pads; and

a wiring pattern provided between the adjacent first pads.

5. The electronic component integrated substrate according to claim 1 , further comprising a second connection pad for being electrically connected to the electronic component at a same layer level as the first pad,

wherein the first solder resist layer is formed on the second connection pad and is provided with a third open portion that selectively exposes the second connection pad, and

wherein the electronic component is electrically connected to the second connection pad via a conductive material provided in the third open portion.

6. The electronic component integrated substrate according to claim 1 ,

wherein the substrate connection member includes a core and a conductive material that covers a circumferential surface of the core, and

wherein the core contacts the connection pad and the second pad, respectively.

7. The electronic component integrated substrate according to claim 1 ,

wherein the electronic component is a semiconductor chip, and

wherein the semiconductor chip is flip-chip mounted while facing a circuit forming surface to the first substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2017
From: SHIRAKI, SATOSHI; TANAKA, KOICHI
To: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Reel/Frame 041014/0764 →
Priority Claims (1)
JP 2016-014726 · Jan 28, 2016 · national
Continuity (1)
Related Publication 20170221829A1 · Aug 3, 2017