Radio frequency transistor stack with improved linearity

1. An RF transistor stack comprising:

a first transistor having a T-gate layout configuration, the first transistor having a body region a plurality of drain regions and a plurality of source regions;

a second transistor having a T-gate layout configuration the second transistor having a body region, a plurality of drain regions, and a plurality of source regions, wherein the orientation of the second transistor is a mirror orientation of the first transistor; and

an interconnect operably coupling the source regions of the first transistor with the drain regions of the second transistor such that the first and second transistors operate in a pair to form a stacked switching element having an on state and an off state, the interconnect not crossing the gate and body regions of the first and second transistors, the stacked switching element being configured to divide an RF voltage across the first and second transistors as result of the mirror orientation of the first and second transistors such that a distortion due to asymmetry in the division of RF voltage between a drain to body and a source to body terminals of the first transistor is cancelled by reversing the asymmetry in the division of the RF voltage in the second transistor when the switching element is in the off state.

2. An RF transistor stack as claimed in claim 1 , wherein the first and second transistors are arranged in the stack such that the first and second transistors have a 180° opposite orientation.

3. An RF transistor stack as claimed in claim 1 , wherein the interconnect between the first and second transistors is orthogonal to respective conductive layers providing gate and body bias to the first and second transistors.

4. An RF transistor stack as claimed in claim 1 , wherein the reversal of asymmetry in the RF voltage is achieved by reversing the asymmetry of the parasitic layout capacitances.

5. An RF transistor stack as claimed in claim 1 , wherein the reversal of asymmetry in the RF voltage is achieved by reversing the asymmetry of the parasitic layout capacitances Cdb, Cbs and by reversing the asymmetry of the layout capacitances Cdg, Cgs.

6. An RF transistor stack as claimed in claim 1 , wherein the first transistor has an associated lateral isolation.

7. An RF transistor stack as claimed in claim 1 , wherein the second transistor has an associated laterial isolation.

8. An RF transistor stack as claimed in claim 1 , wherein first transistor and the second transistor are separate transistors which are operably coupled together during fabrication of the stack.

9. An RF transistor as claimed in claim 1 , wherein two or more transistors are provided in the stack.

10. A semiconductor substrate having an RF transistor stack fabricated thereon, wherein the RF transistor stack comprises:

a first transistor having a T-gate layout configuration the first transistor having a body region, a plurality of drain regions, and a plurality of source regions;

a second transistor having a T-gate layout configuration, the second transistor having a body region, a plurality of drain regions, and a plurality of source regions, wherein the orientation of the second transistor is a mirror orientation of the first transistor; and

an interconnect operably coupling the source regions of the first transistor with the drain regions of the second transistor such that the first and second transistors operate in a pair to form a stacked switching element having an on state and an off state, the interconnect not crossing the gate and body regions of the first and second transistors, the stacked switching element being configured to divide an RF voltage across the first and second transistors as result of the mirror orientation of the first and second transistors such that a distortion due to asymmetry in the division of RF voltage between a drain to body and a source to body terminals of the first transistor is cancelled by reversing the asymmetry in the division of the RF voltage in the second transistor when the switching element is the off state.

11. A method of fabricating an RF transistor stack, the method comprising:

providing a first transistor having a T-gate layout configuration, the first transistor having a body region, a plurality of drain regions, and a plurality of source regions;

providing a second transistor having a T-gate layout configuration the second transistor having a body region, a plurality of drain regions and a plurality of source regions, wherein the orientation of the second transistor is a mirror orientation of the first transistor; and

providing an interconnect operably coupling the source regions of the first transistor with the drain regions of the second transistor such that the first and second transistors operate in a pair to form a stacked switching element having an on state and an off state, the interconnect not crossing the gate and body regions of the first and second transistors, the stacked switching element being configured to divide an RF voltage across the first and second transistors as result of the mirror orientation of the first and second transistors such that a distortion due to asymmetry in the division of RF voltage between a drain to body and a source to body terminals of the first transistor is cancelled by reversing the asymmetry in the division of the RF voltage in the second transistor.