IP Library Granted Patent US 9,935,129
Granted Patent B2
US 9,935,129 · App. 15/621,432 · Granted Apr 3, 2018

Semiconductor device, electronic component, and electronic device

Inventors: Kei Takahashi (Kanagawa, JP); Hiroyuki Miyake (Kanagawa, JP); Hidekazu Miyairi (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/1225G09G3/3291G09G3/3688G09G2300/0838G09G2300/0871G09G2310/027G09G2310/0289G09G2310/0291G09G2330/04
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Quick Facts
Patent No.
US 9,935,129
App. No.
15/621,432
Granted
Apr 3, 2018
Kind
B2
Abstract

To provide a semiconductor device including a small-area circuit with high withstand voltage, an oxide semiconductor (OS) transistor is used as some of transistors included in a circuit handling an analog signal in a circuit to which high voltage is applied. The use of an OS transistor with high withstand voltage as a transistor requiring resistance to high voltage enables the circuit area to be reduced without lowering the performance, as compared to the case using a Si transistor. Furthermore, an OS transistor can be provided over a Si transistor, so that transistors using different semiconductor layers can be stacked, resulting in a much smaller circuit area.

Claims (25)

1. A semiconductor device comprising:

a first circuit configured to generate voltages;

a second circuit configured to convert a first signal into a second signal; and

a third circuit configured to amplify the second signal,

wherein the second circuit comprising first to sixth transistors,

wherein one of a source and a drain of the first transistor, one of a source and a drain of the second transistor, one of a source and a drain of the third transistor, and one of a source and a drain of the fourth transistor are electrically connected to the first circuit,

wherein one of a source and a drain of the fifth transistor is electrically connected to the other of the source and the drain of the first transistor and the other of the source and the drain of the second transistor,

wherein one of a source and a drain of the sixth transistor is electrically connected to the other of the source and the drain of the third transistor and the fourth transistor,

wherein the other of the source and the drain of the fifth transistor and the other of the source and the drain of the sixth transistor are electrically connected to the third circuit,

wherein a gate of the first transistor and a gate of the third transistor are electrically connected to a first wiring,

wherein a gate of the second transistor and a gate of the fourth transistor are electrically connected to a second wiring,

wherein a gate of the fifth transistor is electrically connected to a third wiring, and

wherein each of the first, second, and fifth transistors comprises a semiconductor layer comprising an oxide semiconductor.

2. The semiconductor device according to claim 1 , wherein the first to third wirings are configured to transmit different voltages.

3. The semiconductor device according to claim 1 , further comprising:

a fourth circuit configured to boost a voltage of the first signal,

wherein the fourth circuit is electrically connected to the gates of the first to sixth transistors.

4. The semiconductor device according to claim 1 , wherein the oxide semiconductor comprises In, Ga, and Zn.

5. The semiconductor device according to claim 1 , wherein each of the third, fourth, and sixth transistors comprises a semiconductor layer comprising silicon.

6. An electronic component comprising:

the semiconductor device according to claim 1 ; and

a bump terminal electrically connected to the semiconductor device.

7. An electronic device comprising:

the electronic component according to claim 6 ; and

a display device.

Priority Claims (1)
JP 2014-044471 · Mar 7, 2014 · national
Continuity (2)
Continuation 14633220 · Feb 27, 2015
Related Publication 20170278876A1 · Sep 28, 2017