IP Library › Granted Patent US 9,941,000

Granted Patent B2

US 9,941,000 · App. 15/282,231 · Granted Apr 10, 2018

Memory unit and method of operating a memory unit sector

Inventor: Martin Perner (Munich, DE)

Assignee: Infineon Technologies AG

G11C11/5642 G11C11/5628 G11C11/5635 G11C16/08 G06F11/1068 G06F11/2094 G06F2201/82 G11C29/52 G11C2211/5641

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Quick Facts

Patent No.: US 9,941,000
App. No.: 15/282,231
Granted: Apr 10, 2018
Kind: B2

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Abstract

Disclosed is a memory unit that includes a sector of memory cells. The sector includes a first memory cell configured to selectively take on a state representation of a first plurality of state representations and a second memory cell configured to selectively take on at least one of a second plurality of state representations. The second plurality of state representations is different than the first plurality of state representations. An apparatus includes a processing unit and a memory unit coupled to the processing unit. The memory unit includes a sector of memory cells. Further disclosed are a method of operating a memory unit sector and a method of controlling a sector of a memory unit.

Claims (70)

1. A memory unit, comprising:

a sector of memory cells, wherein the sector includes a first memory cell configured to selectively take on a state representation of a first plurality of state representations and includes a second memory cell configured to selectively take on at least one of a second plurality of state representations,

wherein the second plurality of state representations are different than the first plurality of state representations, and

wherein the second memory cell is preset to a reference representation selected in the second plurality of state representations to represent a predetermined logic state.

2. A memory unit, comprising:

wherein the second plurality of state representations are different than the first plurality of state representations,

wherein the second memory cell is preset to a reference representation selected in the second plurality of state representations to represent a predetermined logic state, and

wherein the sector comprises a first wordline, a first bitline and a third line, wherein the first memory cell is coupled to the first wordline and the first bitline, wherein the second memory cell is coupled to either the first wordline or the first bitline, and wherein the second memory cell is coupled to the third line.

3. A memory unit, comprising:

wherein the second plurality of state representations are different than the first plurality of state representations,

wherein the second memory cell is preset to a reference representation selected in the second plurality of state representations to represent a predetermined logic state, and

wherein at least one first voltage threshold that separates a representation of one logic state from a representation of another logic state is associated with the first plurality of state representations, wherein at least one second voltage threshold that separates the representation of the one logic state from the representation of the another logic state is associated with the second plurality of state representations, and wherein the at least one second voltage threshold is not equal to the at least one first voltage threshold.

4. A memory unit, comprising:

wherein the second plurality of state representations are different than the first plurality of state representations,

wherein the second memory cell is preset to a reference representation selected in the second plurality of state representations to represent a predetermined logic state, and

wherein the first plurality of state representations represent a greater number of logic states than the second plurality of state representations.

5. A memory unit, comprising:

wherein the second plurality of state representations are different than the first plurality of state representations,

wherein the second memory cell is preset to a reference representation selected in the second plurality of state representations to represent a predetermined logic state,

wherein the first memory cell and the second memory cell include a control node and are configured to represent logic states by an amount of cell current responsive to a read voltage provided to the control node,

wherein one of at least two logic states is represented by the amount of cell current for the first memory cell being equal to zero,

wherein a second one of the at least two logic states is represented by the amount of cell current for the first memory cell being equal to or greater than a predetermined non-zero minimum current, and

wherein the second plurality of state representations differs from the first plurality of state representations by a predetermined threshold voltage and a range of read voltages that cause the cell current to be non-zero.

6. The memory unit of claim 1 , wherein the second memory cell is non-volatile.

7. A memory unit, comprising:

wherein the second plurality of state representations are different than the first plurality of state representations,

wherein the second memory cell is preset to a reference representation selected in the second plurality of state representations to represent a predetermined logic state,

wherein the sector comprises a first wordline, a first bitline and a third line, wherein the first memory cell is coupled to the first wordline and the first bitline, wherein the second memory cell is coupled to either the first wordline or the first bitline, wherein the second memory cell is coupled to the third line, and

wherein the third line is a second bitline.

8. A memory unit, comprising:

wherein the second plurality of state representations are different than the first plurality of state representations,

wherein the second memory cell is preset to a reference representation selected in the second plurality of state representations to represent a predetermined logic state,

wherein the sector comprises a first wordline, a first bitline and a third line, wherein the first memory cell is coupled to the first wordline and the first bitline, wherein the second memory cell is coupled to either the first wordline or the first bitline, wherein the second memory cell is coupled to the third line, and

wherein the third line is a second wordline.

9. An apparatus, comprising:

a processing unit; and

10. An apparatus, comprising:

a processing unit; and

a memory unit coupled to the processing unit, wherein the memory unit includes a sector of memory cells, wherein a first memory cell is configured to selectively represent a first plurality of state representations and a second memory cell is configured to selectively represent a second plurality of state representations, wherein the second plurality of state representations are different than the first plurality of state representations, wherein the processing unit is configured to control the first memory cell based on a detected second cell logic state, wherein the second cell is preset to a reference logic state, and wherein at least one first voltage threshold that separates a representation of one logic state from the representation of another logic state is associated with the first plurality of state representations, wherein at least one second voltage threshold that separates the representation of the one logic state from the representation of the another logic state is associated with the second plurality of state representations, and wherein the at least one second voltage threshold is not equal to the at least one first voltage threshold.

11. An apparatus, comprising:

a processing unit; and

12. An apparatus, comprising:

a processing unit; and

13. The apparatus of claim 9 , wherein the second memory cell is non-volatile.

14. An apparatus, comprising:

a processing unit; and

15. An apparatus, comprising:

a processing unit; and

a memory unit coupled to the processing unit, wherein the memory unit includes a sector of memory cells, wherein a first memory cell is configured to selectively represent a first plurality of state representations and a second memory cell is configured to selectively represent a second plurality of state representations, wherein the second plurality of state representations are different than the first plurality of state representations, wherein the processing unit is configured to control the first memory cell based on a detected second cell logic state, wherein the second cell is preset to a reference logic state, wherein the sector comprises a first wordline, a first bitline and a third line, wherein the first memory cell is coupled to the first wordline and to the first bitline, wherein the second memory cell is coupled to one of the first wordline and the first bitline, wherein the second memory cell is coupled to the third line, and wherein the third line is one of a second bitline and a second wordline.

16. A memory unit, comprising:

wherein the second plurality of state representations are different than the first plurality of state representations,

wherein the second memory cell is preset to a reference representation selected in the second plurality of state representations to represent a predetermined logic state, and

wherein the second plurality of state representations represent a greater number of logic states than the first plurality of state representations.

17. The memory unit, wherein the first memory cell and the second memory cell comprise floating-gate transistors.

18. The memory unit, wherein the first memory cell comprises a floating gate transistor and the second memory cell comprises a non-volatile memory cell.

19. The apparatus of claim 9 ,

a processing unit; and

a memory unit coupled to the processing unit, wherein the memory unit includes a sector of memory cells, wherein a first memory cell is configured to selectively represent a first plurality of state representations and a second memory cell is configured to selectively represent a second plurality of state representations, wherein the second plurality of state representations are different than the first plurality of state representations, wherein the processing unit is configured to control the first memory cell based on a detected second cell logic state, wherein the second cell is preset to a reference logic state, and wherein the first memory cell and the second memory cell include a control node and are configured to represent logic states by an amount of cell current responsive to a read voltage provided to the control node, wherein one of at least two logic states is represented by the amount of cell current for the first memory cell being equal to zero, wherein a second one of the at least two logic states is represented by the amount of cell current for the first memory cell being equal to or greater than a predetermined non-zero minimum current, and wherein the second plurality of state representations differs from the first plurality of state representations by a predetermined threshold voltage and a range of read voltages that cause the cell current to be non-zero.

20. The apparatus of claim 9 , wherein the first memory cell and the second memory cell comprise floating-gate transistors.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2016

From: PERNER, MARTIN

To: INFINEON TECHNOLOGIES AG

Reel/Frame 040062/0187 →

Priority Claims (1)

DE 10 2015 116 688 · Oct 1, 2015 · national

Continuity (1)

Related Publication 20170098472A1 · Apr 6, 2017