IP Library Granted Patent US 9,941,229
Granted Patent B2
US 9,941,229 · App. 14/069,361 · Granted Apr 10, 2018

Device including semiconductor chips and method for producing such device

Inventors: Petteri Palm (Regensburg, DE); Thorsten Scharf (Regensburg, DE)
Assignee: Infineon Technologies AG
H01L24/06H01L24/19H01L24/83H01L2224/06182H01L2224/8019H01L2224/83192H01L2924/12042H01L2924/13055H01L2924/13091H01L2924/15747
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Quick Facts
Patent No.
US 9,941,229
App. No.
14/069,361
Granted
Apr 10, 2018
Kind
B2
Abstract

A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

Claims (39)

1. A device, comprising:

a first semiconductor chip manufactured from a semiconductor material and comprising a first face, wherein a first contact pad is arranged over the first face of the first semiconductor chip; and

a second semiconductor chip manufactured from a semiconductor material and comprising a first face, wherein a first contact pad is arranged over the first face of the second semiconductor chip,

wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction,

wherein the first semiconductor chip is located laterally outside of an outline of the second semiconductor chip,

wherein at least one of the first semiconductor chip and the second semiconductor chip comprises a power semiconductor, and

wherein the first semiconductor chip comprises a second contact pad arranged over a second face of the first semiconductor chip opposite to the first face of the first semiconductor chip.

2. The device of claim 1 , wherein the first face of the first semiconductor chip and a second face of the second semiconductor chip, opposite to the first face of the second semiconductor chip, are arranged on different heights.

3. The device of claim 1 , wherein the first and second semiconductor chips are each integrated circuit semiconductor chips.

4. The device of claim 1 , wherein the semiconductor material is an electronic grade semiconductor material.

5. The device of claim 1 , wherein the first semiconductor chip comprises a first integrated circuit arranged in the semiconductor material of the first semiconductor chip, and the second semiconductor chip comprises a second integrated circuit arranged in the semiconductor material of the second semiconductor chip.

6. The device of claim 5 , wherein the first contact pad of the first semiconductor chip provides an electrical connection to the first integrated circuit, and the first contact pad of the second semiconductor chip provides an electrical connection to the second integrated circuit.

7. The device of claim 1 , further comprising:

a material layer, wherein the first semiconductor chip and the second semiconductor chip are at least partly embedded in the material layer.

8. The device of claim 7 , wherein the material layer comprises at least one of a laminate, an epoxy, a filled epoxy, glass fiber filled epoxy, an imide, a thermoplast and a duroplast polymer or polymer blends.

9. The device of claim 1 , further comprising:

a patterned electrically conductive layer arranged over a second face of the first semiconductor chip opposite to the first face of the first semiconductor chip and electrically coupled to the second contact pad of the first semiconductor chip by one of a plated connection and a microvia array or through one or multiple openings over the second contact pad.

10. The device of claim 9 , wherein the patterned electrically conductive layer is arranged over the first face of the second semiconductor chip and electrically coupled to the first contact pad of the second semiconductor chip by a via connection.

11. A device, comprising:

a first semiconductor chip manufactured from a semiconductor material and comprising a first face, wherein a first contact pad is arranged over the first face of the first semiconductor chip; and

a second semiconductor chip manufactured from a semiconductor material and comprising a first face, wherein a first contact pad

is arranged over the first face of the second semiconductor chip,

wherein the first semiconductor chip is located laterally outside of an outline of the second semiconductor chip,

wherein a thickness of the first semiconductor chip is different from a thickness of the second semiconductor chip, and

wherein the first semiconductor chip comprises a second contact pad arranged over a second face of the first semiconductor chip opposite to the first face of the first semiconductor chip.

12. The device of claim 11 , wherein the first face of the first semiconductor chip and a second face of the second semiconductor chip, opposite to the first face of the second semiconductor chip, are arranged on different heights.

13. The device of claim 11 , further comprising:

a material layer, wherein the first semiconductor chip and the second semiconductor chip are at least partly embedded in the material layer.

14. The device of claim 13 , further comprising:

a patterned electrically conductive layer arranged over a second face of the first semiconductor chip opposite to the first face of the first semiconductor chip and electrically coupled to the second contact pad of the first semiconductor chip by one of a plated connection and a microvia array or through one or multiple openings over the second contact pad,

wherein the patterned electrically conductive layer is arranged over the first face of the second semiconductor chip and electrically coupled to the first contact pad of the second semiconductor chip by a via connection.

15. The device of claim 11 , wherein the first and second semiconductor chips are each integrated circuit semiconductor chips.

16. A device, comprising:

a first semiconductor chip manufactured from a semiconductor material and comprising a first face and a second face, the second face on an opposite side of the first semiconductor chip than the first face of the first semiconductor chip, wherein a first contact pad is arranged over the first face of the first semiconductor chip, and wherein a second contact pad is arranged over the second face of the first semiconductor chip; and

a second semiconductor chip manufactured from a semiconductor material and comprising a first face, wherein a first contact pad is arranged over the first face of the second semiconductor chip,

a conductive layer arranged over the first face of the first semiconductor chip, the conductive layer further arranged over the second face of the second semiconductor chip, the conductive layer coupled to the first and second semiconductor chips,

wherein the first semiconductor chip is located laterally outside of an outline of the second semiconductor chip, and

wherein a thickness of the first semiconductor chip is different from a thickness of the second semiconductor chip.

17. The device of claim 16 , wherein the first and second semiconductor chips are each integrated circuit semiconductor chips.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 3, 2013
From: PALM, PETTERI; SCHARF, THORSTEN
To: INFINEON TECHNOLOGIES AG
Reel/Frame 031706/0001 →
Continuity (1)
Related Publication 20150115475A1 · Apr 30, 2015