Multi-wafer stacking by Ox-Ox bonding
A stacked semiconductor device and a method of forming the stacked semiconductor device are provided. A plurality of integrated circuits are bonded to one another to form the stacked semiconductor device. After each bonding step to bond an additional integrated circuit to a stacked semiconductor device formed at the previous bonding step, a plurality of conductive plugs are formed to electrically interconnect the additional integrated circuit to the stacked semiconductor device formed at the previous bonding step.
1. A semiconductor device comprising:
a first workpiece comprising:
a first substrate; and
first metallization layers on a front side of the first substrate, the first metallization layers having a first interconnect;
a second workpiece bonded to the first workpiece, the second workpiece comprising:
a second substrate; and
second metallization layers on a front side of the second substrate, the second metallization layers having a second interconnect, wherein the front side of the second substrate faces the front side of the first substrate;
a first redistribution layer (RDL) on a backside of the second substrate, the backside of the second substrate being opposite the front side of the second substrate;
a first conductive plug extending from the backside of the second substrate to the first interconnect, wherein the first conductive plug extends through the second interconnect, wherein the first conductive plug has a first width as it extends from the backside of the second substrate to the front side of the second substrate, a second width as it extends from the front side of the second substrate to the second interconnect and a third width as it extends from the second interconnect to the first interconnect, wherein the first width is greater than the second width, wherein the second width is greater than the third width, and wherein the first conductive plug narrows as it extends through the second interconnect toward to the first interconnect;
a third workpiece bonded to the second workpiece, the third workpiece comprising:
a third substrate; and
third metallization layers on a front side of the third substrate, the third metallization layers having a third interconnect, wherein the front side of the third substrate faces the backside of the second substrate; and
a second conductive plug extending from a backside of the third substrate to the first RDL, the second conductive plug extending through the third interconnect, the backside of the third substrate being opposite the front side of the third substrate.
2. The semiconductor device of claim 1 , further comprising a second RDL on the backside of the third substrate, the second RDL being in electrical contact with the second conductive plug.
3. The semiconductor device of claim 1 , wherein the first conductive plug is in electrical contact with the first RDL, the first interconnect, and the second interconnect.
4. The semiconductor device of claim 1 , wherein the second conductive plug is in electrical contact with the first RDL and the third interconnect.
5. The semiconductor device of claim 1 , wherein the second interconnect has an annular shape as viewed from top.
6. The semiconductor device of claim 1 , further comprising a third conductive plug extending from the backside of the second substrate to a fourth interconnect of the second metallization layers, the third conductive plug being in electrical contact with the first RDL and the fourth interconnect.
7. The semiconductor device of claim 6 , wherein the third conductive plug has a first width as it extends from the backside of the second substrate to the front side of the second substrate and has a second width as it extends from the front side of the second substrate to the fourth interconnect in the second metallization layers, the second width being smaller than the first width.
8. A semiconductor device comprising:
a first workpiece comprising:
a first substrate;
first dielectric layers on a front side of the first substrate; and
a first interconnect within the first dielectric layers;
a second workpiece stacked atop the first workpiece, the second workpiece comprising:
a second substrate;
second dielectric layers on a front side of the second substrate, wherein the front side of the first substrate faces the front side of the second substrate; and
a second interconnect within the second dielectric layers;
a first redistribution layer (RDL) on a backside of the second substrate, the backside of the second substrate being opposite the front side of the second substrate;
a first conductive plug extending from the backside of the second substrate to the first interconnect, the first conductive plug electrically interconnecting the first RDL, the first interconnect, and the second interconnect, wherein the first conductive plug has a first width within the second substrate, a second width within the second interconnect, and a third width within the first dielectric layers, wherein the first width is greater than the second width, and wherein the second width is greater than the third width;
a third workpiece stacked atop the second workpiece, the third workpiece comprising:
a third substrate;
third dielectric layers on a frond side of the third substrate; and
a third interconnect within the third dielectric layers, wherein the front side of the third substrate faces the backside of the second substrate; and
a second conductive plug extending from a backside of the third substrate to the first RDL, the second conductive plug electrically interconnecting the first RDL and the third interconnect, the backside of the third substrate being opposite the front side of the third substrate.
9. The semiconductor device of claim 8 , further comprising a second RDL on the backside of the third substrate, wherein the second conductive plug is electrically interposed between the second RDL and the third interconnect.
10. The semiconductor device of claim 9 , wherein the first RDL is electrically interconnected with the second RDL.
11. The semiconductor device of claim 8 , wherein the first conductive plug is laterally displaced from the second conductive plug.
12. The semiconductor device of claim 8 , wherein the second interconnect has an annular shape as viewed from top.
13. The semiconductor device of claim 8 , further comprising a third conductive plug extending from the first RDL to a fourth interconnect within the second dielectric layers, the third conductive plug providing electrical contact between the first RDL and the fourth interconnect.
14. The semiconductor device of claim 13 , wherein the third conductive plug has a first width as it extends through the second substrate and has a second width as it extends through a first dielectric layer of the second dielectric layers, the first dielectric layer being a dielectric layer closest to the second substrate, the second width being smaller than the first width.
15. A semiconductor device comprising:
a first workpiece comprising:
a first substrate;
a first conductive feature on a front side of the first substrate; and
a first insulating layer on the front side of the first substrate, the first conductive feature being interposed between the first substrate and the first insulating layer;
a second workpiece bonded to the first workpiece, the second workpiece comprising:
a second substrate;
a second conductive feature on a front side of the second substrate; and
a second insulating layer on the front side of the second substrate, the second conductive feature being interposed between the second substrate and the second insulating layer, the second insulating layer physically contacting the first insulator layer;
a first redistribution layer (RDL) on a backside of the second substrate, the backside of the second substrate being opposite the front side of the second substrate;
a first conductive plug extending from the backside of the second substrate to the first conductive feature, wherein the first conductive plug has a first width as it extends from the backside of the second substrate to the front side of the second substrate, a second width as it extends from the front side of the second substrate to the second conductive feature, a third width as it extends through the first insulating layer and the second insulating layer, and the second width and the third width as it extends through the second conductive feature, wherein the first width is greater than the second width, and wherein the second width is greater than the third width;
a third workpiece bonded to the second workpiece, the third workpiece comprising:
a third substrate;
a third conductive feature on a front side of the third substrate; and
a third insulating layer on the front side of the third substrate, the third conductive feature being interposed between the third substrate and the third insulating layer, the third insulating layer physically contacting the first RDL; and
a second conductive plug extending from a backside of the third substrate to the first RDL, the backside of the third substrate being opposite the front side of the third substrate.
16. The semiconductor device of claim 15 , further comprising a third conductive plug extending from the first RDL to a fourth conductive feature on the front side of the second substrate, the fourth conductive feature being interposed between the second substrate and the second insulating layer.
17. The semiconductor device of claim 16 , wherein the first RDL electrically couples the second conductive plug and the third conductive plug.
18. The semiconductor device of claim 15 , wherein the first RDL electrically couples the first conductive plug and the second conductive plug.
19. The semiconductor device of claim 15 , wherein the second conductive feature has an annular shape as viewed from top.
20. The semiconductor device of claim 15 , further comprising a second RDL on the backside of the third substrate, wherein the second conductive plug electrically couples the first RDL and the second RDL.