IP Library › Granted Patent US 9,941,275
Granted Patent B2
US 9,941,275 · App. 15/470,872 · Granted Apr 10, 2018

3D semiconductor device and structure

Inventors: Zvi Or-Bach (San Jose, CA); Brian Cronquist (San Jose, CA); Deepak Sekar (San Jose, CA)
Assignee: MONOLITHIC 3D INC.
H01L27/0688H01L23/3677H01L23/544H01L23/562H01L23/585H01L27/088H01L27/092H01L2223/54426H01L2223/54453
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Quick Facts
Patent No.
US 9,941,275
App. No.
15/470,872
Granted
Apr 10, 2018
Kind
B2
Abstract

An Integrated Circuit device, including: a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single crystal transistors, where the second layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of the first transistors that cross the first dice lane, where a plurality of the second transistors are circumscribed by a second dice lane of at least 10 microns width, and there are no second conductive connections to the plurality of the second transistors that cross the second dice lane, and at least one thermal conducting path from at least one of the second single crystal transistors to an external surface of the device.

Claims (94)

1. An Integrated Circuit device, comprising:

a first layer comprising first single crystal transistors;

a second layer overlaying said first layer, said second layer comprising second single crystal transistors,

wherein said second layer thickness is less than one micron,

wherein a plurality of said first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to said plurality of said first transistors that cross said first dice lane,

wherein a plurality of said second transistors are circumscribed by a second dice lane of at least 10 microns width, and there are no second conductive connections to said plurality of said second transistors that cross said second dice lane, and

wherein said second dice lane is overlaying and aligned to said first dice lane; and

at least one thermal conducting path from at least one of said second single crystal transistors to an external surface of said device.

2. An Integrated Circuit device, comprising:

a first layer comprising first single crystal transistors;

a second layer overlaying said first layer, said second layer comprising second single crystal transistors,

wherein said second layer thickness is less than one micron,

wherein a plurality of said first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to said plurality of said first transistors that cross said first dice lane,

wherein a plurality of said second transistors are circumscribed by a second dice lane of at least 10 microns width, and there are no second conductive connections to said plurality of said second transistors that cross said second dice lane, and

wherein said second dice lane is overlaying and aligned to said first dice lane; and

at least one thermal conducting path from at least one of said second single crystal transistors to an external surface of said device; and

a third layer comprising third single crystal transistors.

3. An Integrated Circuit device, comprising:

a first layer comprising first single crystal transistors;

a second layer overlaying said first layer, said second layer comprising second single crystal transistors,

wherein said second layer thickness is less than one micron,

wherein a plurality of said first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to said plurality of said first transistors that cross said first dice lane,

wherein a plurality of said second transistors are circumscribed by a second dice lane of at least 10 microns width, and there are no second conductive connections to said plurality of said second transistors that cross said second dice lane, and

wherein said second dice lane is overlaying and aligned to said first dice lane; and

at least one thermal conducting path from at least one of said second single crystal transistors to an external surface of said device,

wherein said thermal conducting path has a thermal conductivity greater than 20 W/m-K.

4. An Integrated Circuit device, comprising:

a first layer comprising first single crystal transistors;

a second layer overlaying said first layer, said second layer comprising second single crystal transistors,

wherein said second layer thickness is less than one micron,

wherein a plurality of said first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to said plurality of said first transistors that cross said first dice lane,

wherein a plurality of said second transistors are circumscribed by a second dice lane of at least 10 microns width, and there are no second conductive connections to said plurality of said second transistors that cross said second dice lane, and

wherein said second dice lane is overlaying and aligned to said first dice lane; and

at least one thermal conducting path from at least one of said second single crystal transistors to an external surface of said device,

wherein said first single crystal transistors are aligned to said second single crystal transistors with less than 200nm alignment error.

5. A 3D semiconductor device, comprising:

a first layer comprising first single crystal transistors;

a second layer overlying said first single crystal transistors and comprising second single crystal transistors,

wherein said second layer thickness is less than one micron,

wherein a plurality of said first single crystal transistors is circumscribed by a first guard ring,

wherein a plurality of said second single crystal transistors is circumscribed by a second guard ring, and

wherein said second guard ring overlays and is aligned to said first guard ring; and

at least one thermal conducting path from at least one of said second single crystal transistors to an external surface of said device.

6. A 3D semiconductor device, comprising:

a first layer comprising first single crystal transistors;

a second layer overlying said first single crystal transistors and comprising second single crystal transistors,

wherein said second layer thickness is less than one micron,

wherein a plurality of said first single crystal transistors is circumscribed by a first guard ring,

wherein a plurality of said second single crystal transistors is circumscribed by a second guard ring, and

wherein said second guard ring overlays and is aligned to said first guard ring; and

at least one thermal conducting path from at least one of said second single crystal transistors to an external surface of said device,

wherein said thermal conducting path has a thermal conductivity greater than 20 W/m-K.

7. A 3D semiconductor device, comprising:

a first layer comprising first single crystal transistors;

a second layer overlying said first single crystal transistors and comprising second single crystal transistors,

wherein said second layer thickness is less than one micron,

wherein a plurality of said first single crystal transistors is circumscribed by a first guard ring,

wherein a plurality of said second single crystal transistors is circumscribed by a second guard ring, and

wherein said second guard ring overlays and is aligned to said first guard ring; and

at least one thermal conducting path from at least one of said second single crystal transistors to an external surface of said device,

wherein said first single crystal transistors are aligned to said second single crystal transistors with less than 200nm alignment error.

8. A 3D semiconductor device, comprising:

a first layer comprising first single crystal transistors;

a second layer overlying said first single crystal transistors and comprising second single crystal transistors,

wherein said second layer thickness is less than one micron,

wherein a plurality of said first single crystal transistors is circumscribed by a first guard ring,

wherein a plurality of said second single crystal transistors is circumscribed by a second guard ring, and

wherein said second guard ring overlays and is aligned to said first guard ring; and

at least one thermal conducting path from at least one of said second single crystal transistors to an external surface of said device,

wherein the majority of the transistors comprised in said second layer have a thermal conducting path to said external surface.

9. A 3D semiconductor device, comprising:

a first structure comprising first single crystal transistors;

a second structure overlying said first single crystal transistors and comprising second single crystal transistors,

wherein at least one of said second single crystal transistors is at least partially self-aligned to at least one of said first single crystal transistors; and

at least one thermal conducting path from at least one of said second single crystal transistors to an external surface of said device.

10. A 3D semiconductor device, comprising:

a first structure comprising first single crystal transistors;

a second structure overlying said first single crystal transistors and comprising second single crystal transistors,

wherein at least one of said second single crystal transistors is at least partially self-aligned to at least one of said first single crystal transistors; and

at least one thermal conducting path from at least one of said second single crystal transistors to an external surface of said device,

wherein a plurality of said first single crystal transistors is circumscribed by a first guard ring, and plurality of said second single crystal transistors is circumscribed by a second guard ring, and

wherein said second guard ring overlays and is aligned to said first guard ring.

11. A 3D semiconductor device, comprising:

a first structure comprising first single crystal transistors;

a second structure overlying said first single crystal transistors and comprising second single crystal transistors,

wherein at least one of said second single crystal transistors is at least partially self-aligned to at least one of said first single crystal transistors; and

at least one thermal conducting path from at least one of said second single crystal transistors to an external surface of said device; and

a third structure comprising third single crystal transistors, said a portion of said third single crystal transistors form a logic circuit.

12. A 3D semiconductor device, comprising:

a first structure comprising first single crystal transistors;

a second structure overlying said first single crystal transistors and comprising second single crystal transistors,

wherein at least one of said second single crystal transistors is at least partially self-aligned to at least one of said first single crystal transistors; and

at least one thermal conducting path from at least one of said second single crystal transistors to an external surface of said device,

wherein said thermal conducting path has a thermal conductivity greater than 20 W/m-K.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 22, 2017
From: OR-BACH, ZVI; SEKAR, DEEPAK; CRONQUIST, BRIAN
To: MONOLITHIC 3D INC.
Reel/Frame 044203/0276 →
Continuity (5)
Continuation In Part 13864245 · Apr 17, 2013
Continuation 13803437 · Mar 14, 2013
Continuation In Part 13731108 · Dec 30, 2012
Continuation 13730897 · Dec 29, 2012
Related Publication 20170200716A1 · Jul 13, 2017