Organic light-emitting diode display and method of manufacturing the same

1. An organic light-emitting diode (OLED) display, comprising:

a substrate comprising a display area configured to display an image and a peripheral area surrounding the display area;

a thin film transistor (TFT) formed in the display area over the substrate;

a first planarization layer covering the TFT in the display area;

an OLED formed over the first planarization layer and electrically connected to the TFT; and

a second planarization layer formed in the peripheral area, wherein the second planarization layer includes a plurality of out-gassing holes formed therein,

wherein at least a portion of the second planarization layer is thinner than the first planarization layer, and

wherein the out-gassing holes are configured to discharge a residual gas from the second planarization layer, and no layer is disposed on the out-gassing holes.

2. The OLED display of claim 1 , wherein the plurality of out-gassing holes are formed in the portion of the second planarization layer.

3. The OLED display of claim 2 , wherein the width between a pair of adjacent ones of the out-gassing holes is in the range of about 400 μm to about 700 μm.

4. The OLED display of claim 3 , further comprising a plurality of wires formed in the peripheral area over the substrate, wherein the second planarization layer covers the wires, and

wherein at least one of the wires is positioned between the pair of adjacent out-gassing holes.

5. The OLED display of claim 4 , wherein the TFT comprises:

an active layer formed over the substrate;

a gate electrode formed over the active layer; and

source and drain electrodes formed over the gate electrode and electrically connected to the active layer,

wherein the first planarization layer covers the source and drain electrodes, and wherein the source and drain electrodes are formed on the same layer as the wires.

6. The OLED display of claim 5 , wherein the OLED comprises:

a first electrode formed over the first planarization layer and electrically connected to the drain electrode;

a pixel defining layer formed over the first electrode so as to define a pixel area;

an organic emission layer formed over the first electrode and contacting the first electrode in the pixel area; and

a second electrode formed over the organic emission layer.

7. The OLED display of claim 3 , further comprising an alignment mark formed in the peripheral area, wherein the alignment mark is covered by the second planarization layer, and

wherein the alignment mark is positioned between the pair of adjacent out-gassing holes.

8. The OLED display of claim 3 , wherein the width between the pair is greater than the thickness of the second planarization layer and the thickness of the first planarization layer.

9. The OLED display of claim 3 , wherein the width between the pair is greater than the widths of the out-gassing holes.

10. The OLED display of claim 1 , wherein the thickness of the second planarization layer is less than about 5 μm.

11. The OLED display of claim 10 , wherein the thickness of the first planarization layer is in the range of about 6 μm to about 8 μm.

12. The OLED display of claim 1 , wherein the first and second planarization layers are formed on the same layer.

13. An organic light-emitting diode (OLED) display, comprising:

a substrate comprising a display area configured to display an image and a peripheral area surrounding the display area;

an active layer formed in the display area;

a gate electrode formed over the active layer;

an interlayer insulating layer formed over the gate electrode;

source and drain electrodes formed over the interlayer insulating layer and electrically connected to the active layer;

a first planarization layer covering the source and drain electrodes in the display area;

an OLED formed over the first planarization layer and electrically connected to the drain electrode;

an alignment mark covered by the interlayer insulating layer in the peripheral area and configured to align masks during a manufacturing process of the OLED display; and

a second planarization layer formed over the interlayer insulating layer in the peripheral area,

wherein an exposure hole is formed in the second planarization layer so as to expose the interlayer insulating layer formed over the alignment mark,

wherein the exposure hole is configured to discharge a residual gas from the second planarization layer,

wherein the alignment mark is not connected to a separate signal line, and

wherein no layer is disposed on the exposure hole.

14. The OLED display of claim 13 , wherein the alignment mark is formed on the same layer as the gate electrode.