IP Library › Granted Patent US 9,941,362
Granted Patent B2
US 9,941,362 · App. 15/334,356 · Granted Apr 10, 2018

Method of manufacturing silicon carbide semiconductor device

Inventors: Hidenao Kuribayashi (Matsumoto, JP); Masayuki Miyazaki (Matsumoto, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H01L29/1608H01L21/02529H01L21/02609H01L21/02694H01L21/265H01L21/26506H01L21/324H01L29/0615H01L29/32H01L29/36H01L29/66068H01L29/66348H01L29/7397H01L29/78H01L29/861H01L29/868
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Quick Facts
Patent No.
US 9,941,362
App. No.
15/334,356
Granted
Apr 10, 2018
Kind
B2
Abstract

A method of manufacturing a silicon carbide semiconductor device. The method includes providing an n-type semiconductor substrate having first and second principal surfaces, introducing an impurity from a first principal surface of the semiconductor substrate at a first position, activating the impurity to form a diffusion layer in the semiconductor substrate at a second position, implanting protons at a third position that is deeper from the first principal surface than the first position, the protons generating crystal defects in a region through which the protons pass, converting by thermal treating the protons into hydrogen induced donors to form an n-type field stop layer at a fourth position deeper from the first principal surface than the second position, reducing by the thermal treating the generated crystal defects to form an n-type crystal defect reduction region, and forming an electrode on the second principal surface after implanting the protons.

Claims (60)

1. A method of manufacturing a silicon carbide semiconductor device, the method comprising:

providing an n-type semiconductor substrate including silicon carbide, the semiconductor substrate having first and second principle surfaces;

introducing an impurity of a p-type or an n-type from the first principal surface of the n-type semiconductor substrate at a first position;

activating the impurity to form a diffusion layer of the p-type or the n-type in the n-type semiconductor substrate at a second position;

implanting protons at a third position that is deeper from the first principal surface of the n-type semiconductor substrate than the first position, the protons generating crystal defects in a region through which the protons pass;

converting the protons into hydrogen induced donors to form an n-type field stop layer at a fourth position that is deeper from the first principal surface of the n-type semiconductor substrate than the second position;

reducing the crystal defects generated in the proton passing-through region to form an n-type crystal defect reduction region; and

forming an electrode on the second principal surface of the n-type semiconductor substrate, wherein

the protons are implanted before the electrode is formed, and

the converting the protons and the reducing the crystal defects are executed by same thermal treating at a temperature of a range from 900° C. to 1300° C.

2. The method of manufacturing a silicon carbide semiconductor device according to claim 1 , wherein

the thermal treating heats the entire n-type semiconductor substrate.

3. The method of manufacturing a silicon carbide semiconductor device according to claim 2 , wherein

the thermal treating is performed by furnace annealing.

4. The method of manufacturing a silicon carbide semiconductor device according to claim 1 , wherein

the activating the impurity, the converting the protons into the hydrogen induced donors, and the reducing crystal defects are executed by the same thermal treating.

5. The method of manufacturing a silicon carbide semiconductor device according to claim 4 , wherein

the silicon carbide semiconductor device is manufactured by sequentially performing the steps of introducing the impurity, implanting the protons, and performing the thermal treating.

6. The method of manufacturing a silicon carbide semiconductor device according to claim 4 , wherein

the thermal treating heats the proton passing-through region by laser annealing, which is executed by applying a laser light beam from the first principal surface of the n-type semiconductor substrate.

7. The method of manufacturing a silicon carbide semiconductor device according to claim 1 , further comprising

forming, before introducing the impurity, a front surface element structure of an insulated gate bipolar transistor on the second principal surface side of the n-type semiconductor substrate, wherein

the introduced impurity is of the p-type, and

the formed diffusion layer is of the p-type, to thereby form a p-type collector layer.

8. The method of manufacturing a silicon carbide semiconductor device according to claim 1 , further comprising

forming, before introducing the impurity, a front surface element structure of a diode on the second principal surface side of the n-type semiconductor substrate, wherein

the introduced impurity is of the n-type, and

the formed diffusion layer is of the n-type, to thereby form an n-type cathode layer.

9. A method of manufacturing a silicon carbide semiconductor device the method comprising:

providing an n-type semiconductor substrate including silicon carbide, the semiconductor substrate having first and second principle surfaces;

introducing an impurity of a p-type or an n-type from the first principal surface of the n-type semiconductor substrate at a first position;

activating the impurity to form a diffusion layer of the p-type or the n-type in the n-type semiconductor substrate at a second position;

implanting protons at a third position that is deeper from the first principal surface of the n-type semiconductor substrate than the first position, the protons generating crystal defects in a region through which the protons pass;

converting the protons into hydrogen induced donors to form an n-type field stop layer at a fourth position that is deeper from the first principal surface of the n-type semiconductor substrate than the second position;

reducing the crystal defects generated in the proton passing-through region to form an n-type crystal defect reduction region; and

forming an electrode on the second principal surface of the n-type semiconductor substrate, wherein

the protons are implanted before the electrode is formed,

the converting the protons and the reducing the crystal defects are executed by same thermal treating, and

the silicon carbide semiconductor device is manufactured by sequentially performing the steps of introducing the impurity, activating the impurity, implanting the protons, and performing the thermal treating.

10. The method of manufacturing a silicon carbide semiconductor device according to claim 9 , wherein

the activating the impurity includes applying a laser light beam from the first principal surface of the n-type semiconductor substrate, and

the method further includes, after the activating of the impurity, disposing a metal film on the first principal surface of the n-type semiconductor substrate, and forming an ohmic contact with the n-type semiconductor substrate.

11. The method of manufacturing a silicon carbide semiconductor device according to claim 10 , wherein

the disposing the metal film is executed after the thermal treating.

12. The method of manufacturing a silicon carbide semiconductor device according to claim 10 , wherein

the forming the ohmic contact includes performing another thermal treating, which is at a temperature lower than that of the thermal treating.

13. A silicon carbide semiconductor device, comprising:

an n-type semiconductor substrate including silicon carbide, the semiconductor substrate having first and second principle surfaces;

a diffusion layer of a p-type or an n-type formed in the n-type semiconductor substrate at the first principal surface thereof;

an n-type field stop layer formed in the n-type semiconductor substrate, at a position deeper from the first principal surface of the n-type semiconductor substrate than a position of the diffusion layer, the n-type field stop layer having a mountain-shaped impurity concentration distribution, a peak thereof being higher than an impurity concentration of the n-type semiconductor substrate, and being higher than a magnitude difference of the impurity concentration of the n-type semiconductor substrate along a depth direction thereof;

an n-type crystal defect region formed in the n-type semiconductor substrate, at a position shallower from the first principal surface of the n-type semiconductor substrate than the position of the n-type field stop layer, an impurity concentration in the n-type crystal defect region being substantially uniform and being lower than that of the n-type field stop layer, and having more crystal defects than the n-type semiconductor substrate;

an element structure formed on the second principal surface of the n-type semiconductor substrate;

a first electrode contacting the diffusion layer; and

a second electrode formed on the second principal surface of the n-type semiconductor substrate, wherein

the n-type field stop layer includes an n-type semiconductor that has, as donors, the crystal defects including hydrogen atoms, and

carrier mobility of the n-type crystal defect region is equal to or higher than 30%, and equal to or lower than 100%, of carrier mobility of the n-type semiconductor substrate.

14. The silicon carbide semiconductor device according to claim 13 , wherein

the crystal defects in the n-type field stop layer further include vacancies and oxygen atoms.

15. The silicon carbide semiconductor device according to claim 13 , wherein

the n-type field stop layer includes more hydrogen atoms than the n-type crystal defect region does.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2016
From: KURIBAYASHI, HIDENAO; MIYAZAKI, MASAYUKI
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 040132/0309 →
Priority Claims (1)
JP 2014-232711 · Nov 17, 2014 · national
Continuity (2)
Continuation PCTJP2015081907 · Nov 12, 2015
Related Publication 20170047408A1 · Feb 16, 2017