IP Library Granted Patent US 9,946,646
Granted Patent B2
US 9,946,646 · App. 15/256,950 · Granted Apr 17, 2018

Systems and method for delayed cache utilization

Inventor: William L. Walker (Fort Collins, CO)
Assignee: Advanced Micro Devices, Inc.
G06F12/0811G06F12/0831G06F12/128G06F2212/283G06F2212/69
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Quick Facts
Patent No.
US 9,946,646
App. No.
15/256,950
Granted
Apr 17, 2018
Kind
B2
Abstract

A system for managing cache utilization includes a processor core, a lower-level cache, and a higher-level cache. In response to activating the higher-level cache, the system counts lower-level cache victims evicted from the lower-level cache. While a count of the lower-level cache victims is not greater than a threshold number, the system transfers each lower-level cache victim to a system memory without storing the lower-level cache victim to the higher-level cache. When the count of the lower-level cache victims is greater than the threshold number, the system writes each lower-level cache victim to the higher-level cache. In this manner, if the higher-level cache is deactivated before the threshold number of lower-level cache victims is reached, the higher-level cache is empty and thus may be deactivated without flushing.

Claims (66)

1. A method for managing cache utilization in a processing system, the method comprising:

in response to activating a higher-level cache, counting lower-level cache victims evicted from one or more lower-level caches;

while a count of the lower-level cache victims is not greater than a threshold number, storing each lower-level cache victim of the lower-level cache victims to memory without storing the lower-level cache victim to the higher-level cache; and

when the count of the lower-level cache victims is greater than the threshold number, storing each lower-level cache victim evicted after the threshold number was exceeded to the higher-level cache.

2. The method of claim 1 , wherein each of the one or more lower-level caches is a level 2 (L2) cache, and wherein the higher-level cache is a level 3 (L3) cache.

3. The method of claim 1 , wherein the threshold number is static over multiple activations of the higher-level cache.

4. The method of claim 1 , further comprising:

dynamically determining the threshold number based at least in part on at least one of: a cache victim count history of the one or more lower-level caches, a valid bit history of the higher-level cache, an upper constraint on the threshold number, a lower constraint on the threshold number, a power usage of the higher-level cache, or a power down time of the higher-level cache.

5. The method of claim 1 , further comprising:

storing a cache victim history associating a number of cache victims with each time period of a set of time periods of activity of the one or more lower-level caches; and

determining the threshold number based at least in part on the cache victim history.

6. The method of claim 5 , wherein determining the threshold number comprises determining the threshold number based at least in part on an upper constraint on the threshold number.

7. The method of claim 1 , further comprising:

tracking occupied regions of the higher-level cache using valid bits;

storing a history of valid bits associating a usage of valid bits with time periods of activity of the higher-level cache; and

determining the threshold number based at least in part on the history of valid bits.

8. The method of claim 1 , wherein storing each lower-level cache victim evicted after the threshold number was exceeded to the higher-level cache comprises:

selecting a region of the higher-level cache to which a lower-level cache victim is stored based on a way constraint.

9. The method of claim 1 , further comprising:

in response to an indication that the higher-level cache is to be deactivated, selecting a power down procedure for the higher-level cache based at least in part on whether the count of the lower-level cache victims exceeds the threshold number.

10. The method of claim 9 , wherein:

selecting a power down procedure comprises:

selecting a power down procedure in which the higher-level cache is deactivated without flushing the higher-level cache when the count of the lower-level cache victims does not exceed the threshold number.

11. The method of claim 10 , wherein:

selecting a power down procedure comprises selecting a power down procedure in which the higher-level cache is deactivated with flushing of the higher-level cache when the count of the lower-level cache victims exceeds the threshold number.

12. A system comprising:

a processor core;

one or more lower-level caches accessible by the processor core;

a higher-level cache accessible by the processor core and the one or more lower-level caches; and

a controller to access the one or more lower-level caches and the higher-level cache, wherein the controller is to:

in response to activating the higher-level cache, count lower-level cache victims evicted from the one or more lower-level caches;

while a count of the lower-level cache victims is not greater than a threshold number, store each lower-level cache victim of the lower-level cache victims to a system memory without storing the lower-level cache victim to the higher-level cache; and

when the count of the lower-level cache victims is greater than the threshold number, store each lower-level cache victim evicted after the threshold number was exceeded to the higher-level cache.

13. The system of claim 12 , wherein the threshold number is static over multiple activations of the higher-level cache.

14. The system of claim 12 , wherein the controller further is to dynamically determine the threshold number based at least in part on at least one of: a cache victim count history of the one or more lower-level caches, a valid bit history of the one or more lower level caches, an upper constraint on the threshold number, a lower constraint on the threshold number, a power usage of the higher-level cache, or a power down time of the higher-level cache.

15. The system of claim 12 , wherein the controller is to:

store a cache victim history associating a number of cache victims with each time period of a set of time periods of activity of the one or more lower-level caches; and

determine the threshold number based at least in part on the cache victim history.

16. The system of claim 12 , wherein the controller is to track occupied regions of the higher-level cache using valid bits in a tag array of the higher-level cache.

17. The system of claim 16 , wherein the controller is to:

store a history of valid bits associating a usage of the valid bits with time periods of activity of the higher-level cache; and

determine the threshold number based at least in part on the history of valid bits.

18. The system of claim 12 , wherein the controller is to power down the higher-level cache without flushing the higher-level cache when the count of the lower-level cache victims does not exceed the threshold number.

19. The system of claim 12 , wherein the controller is to select a region of the higher-level cache to which a lower-level victim is stored while the count is not greater than the threshold number based on a way constraint.

20. A method for managing cache utilization, the method comprising:

storing a cache victim history associating a number of cache victims with each time period of a set of time periods of lower-level cache activity;

determining a threshold number of lower-level cache victims to be sent to memory without being stored to a higher-level cache; and

in response to activating the higher-level cache, storing up to a threshold number of lower-level cache victims following activating of the higher-level cache to system memory without writing to the higher-level cache.

21. The method of claim 20 , wherein storing up to the threshold number of lower-level cache victims includes determining a count of the lower-level cache victims.

22. The method of claim 21 , wherein storing up to the threshold number of lower-level cache victims further includes, storing each lower-level cache victim of the lower-level cache victims to memory without storing the lower-level cache victim to the higher-level cache while the count of the lower-level cache victims is not greater than the threshold number.

23. A method for managing cache utilization, the method comprising:

in response to activating a higher-level cache, counting lower-level cache victims sent to the higher-level cache; and

while a count of the lower-level cache victims is not greater than a threshold number, storing each lower-level cache victim of the lower-level cache victims to the higher-level cache and storing, in a flush table, a location of the higher-level cache at which the lower-level cache victim is stored.

24. The method of claim 23 , further comprising:

when the count of the lower-level cache victims exceeds the threshold number, writing each lower-level cache victim to the higher-level cache without storing to the flush table a location of the higher-level cache at which the lower-level cache victim is stored.

25. The method of claim 23 , further comprising:

storing a cache victim history associating a number of cache victims with each time period of a set of time periods of activity of the one or more lower-level caches; and

determining the threshold number based at least in part on the cache victim history.

26. The method of claim 23 , further comprising:

deactivating the higher-level cache without flushing the higher-level cache when the count of the lower-level cache victims does not exceed the threshold number.

27. The method of claim 23 , further comprising:

tracking occupied regions of the higher-level cache using valid bits;

storing a history of valid bits associating a usage of valid bits with time periods of activity of the higher-level cache; and

determining the threshold number based at least in part on the history of valid bits.

28. The method of claim 23 , wherein storing each lower-level cache victim evicted after the threshold number was exceeded to the higher-level cache comprises:

selecting a region of the higher-level cache to which a lower-level cache victim is stored based on a way constraint.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2016
From: WALKER, WILLIAM L.
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 039689/0288 →
Continuity (1)
Related Publication 20180067856A1 · Mar 8, 2018