Network controller—sideband interface port controller

1. A network interface controller comprising:

a media access controller (MAC) connected to receive in-band and sideband packets;

a host adapter comprising a receive route connected to receive packets from the media access controller, and further connected to transmit the in-band packets to a host; and

a sideband port controller comprising a sideband receive buffer, wherein the sideband port controller is configured to:

compile information into a set of asynchronous event notification (AEN) packets;

analyze the in-band packets to provide an indication that the in-band packet contains the set of AEN packets; and

forward the set of AEN packets to a sideband endpoint circuit in response to a packet parser providing the indication,

wherein the host adapter further comprises:

a first receive buffer to store a packet from the media access controller;

a packet injection arbiter (PIA) connected to allow, at a time, the in-band packet in the first receive buffer to advance from the first receive buffer along the receive route towards the host and further connected to allow, at a different time, the sideband packet to advance from the first receive buffer to the sideband receive buffer of the sideband port controller, wherein the PIA further comprises a decoder connected to read a header of a packet in the first receive buffer, and in response to reading the header, to route the packet towards the host or the sideband port controller;

an output XS 1 buffer that is selected by the PIA to receive any forwarded packets;

an XS 2 buffer configured to receive data packets that are not in-band data packets or sideband packets from the host into a receive backbone unit, the receive backbone unit being configured to manage movement of data from the MAC by converting, aligning, and storing the data into a line buffer, wherein the XS 2 buffer receives priority over the output XS 1 buffer;

a counter configured to be incremented when the in-band packet is advanced from the output XS 1 buffer to the XS 2 buffer; and

a packet engage latch that is set when either the output XS 1 buffer or the XS 2 buffer is selected to receive any incoming packet.

2. The network interface controller of claim 1 , wherein the host adapter further comprises a second receive buffer on the receive route, the second receive buffer being connected to receive the in-band packets from the first receive buffer.

3. The network interface controller of claim 1 , wherein the sideband port controller is connected to transmit the sideband packets to a sideband endpoint.

4. The network interface controller of claim 1 , wherein at least one AEN packet of the set of AEN packets comprises: a destination address field; a source address field; an Ethernet type field; a media content (MC) identification (ID) field; a header field; a sequence number field; a control packet type field; a channel ID field; a pay load length field; an AEN type field; a payload data field; a checksum field; and a frame check sequence field.

5. The network interface controller of claim 1 , further comprising:

a packet injection register (PIR) that is configured to accept data packets when the PIR has available bandwidth to store in-band packets and sideband packets; and

an end of packet (EOP) marker that is configured to trigger a latch to be set when the PIR has no available bandwidth.