Multichip package link
A system-on-a-chip, such as a logical PHY, may be divided into hard IP blocks with fixed routing, and soft IP blocks with flexible routing. Each hard IP block may provide a fixed number of lanes. Using p hard IP blocks, where each block provides n data lanes, h=n*p total hard IP data lanes are provided. Where the system design calls for k total data lanes, it is possible that k≠h, so that ┌k/n┐ hard IP blocks provide h=n*p available hard IP data lanes. In that case, h−k lanes may be disabled. In cases where lane reversals occur, such as between hard IP and soft IP, bowtie routing may be avoided by the use of a multiplexer-like programmable switch within the soft IP.
1. An apparatus comprising:
an interconnect comprising p hard logic blocks, wherein each hard logic block is to provide n data lanes and is to have a fixed routing, and wherein the p hard logic blocks are to provide h=n*p available hard data lanes, the data lanes having separate per-lane enables; and
a soft computing block comprising routable logic to communicatively couple the interconnect to a host platform and to provide for the interconnect k data lanes, wherein k<h;
wherein k−h lanes are to be disabled via the per-lane enables.
2. The apparatus of claim 1 , wherein the soft computing block further comprises a programmable switch to selectively map data lanes according to a switch mode.
3. The apparatus of claim 2 , wherein the switch mode comprises at least a direct lane mapping mode, in which lanes are to be mapped in numerical order, and a cross-mapping mode, in which lanes are to be mapped in reverse numerical order.
4. The apparatus of claim 2 , wherein the switch mode is programmable via a fuse pull.
5. The apparatus of claim 2 , wherein the switch mode is programmable via a training sequence.
6. The apparatus of claim 2 , wherein the switch mode is programmable via read-only memory.
7. The apparatus of claim 1 , wherein each lane is to receive a non-correlated pseudo-random bit sequence for centering.
8. The apparatus of claim 1 , wherein at least some of the hard logic blocks are to receive a separate VALID signal.
9. The apparatus of claim 1 , wherein at least some of the hard logic blocks are to receive a separate STREAM_ID.
10. The apparatus of claim 1 , wherein the k−h disabled lanes are to be distributed amongst the k data lanes.
11. An interconnected system, comprising:
a first agent;
a second agent; and
an interconnect to communicatively couple the first agent to the second agent, comprising:
p hard logic blocks, wherein each hard logic block is to provide n data lanes and is to have a fixed routing, and wherein the p hard logic blocks are to provide h=n*p available hard data lanes, the data lanes having separate per-lane enables; and
a soft computing block comprising routable logic to communicatively couple the interconnect to a host platform and to provide for the interconnect k data lanes, wherein k<h;
wherein k−h lanes are to be disabled via the per-lane enables.
12. The interconnected system of claim 11 , wherein the soft computing block further comprises a programmable switch to selectively map data lanes according to a switch mode.
13. The interconnected system of claim 12 , wherein the switch mode comprises at least a direct lane mapping mode, in which lanes are to be mapped in numerical order, and a cross-mapping mode, in which lanes are to be mapped in reverse numerical order.
14. The interconnected system of claim 12 , wherein the switch mode is programmable via a fuse pull.
15. The interconnected system of claim 12 , wherein the switch mode is programmable via a training sequence.
16. The interconnected system of claim 12 , wherein the switch mode is programmable via read-only memory.
17. The interconnected system of claim 12 , wherein each lane is to receive a non-correlated pseudo-random bit sequence for centering.
18. The interconnected system of claim 12 , wherein at least some of the hard logic blocks are to receive a separate VALID signal.
19. The interconnected system of claim 12 , wherein at least some of the hard logic blocks are to receive a separate STREAM_ID.
20. The interconnected system of claim 11 , wherein the k−h disabled lanes are to be distributed amongst the k data lanes.
21. A method of provisioning an interconnect, comprising:
placing p hard logic blocks, wherein each hard logic block is to provide n data lanes and is to have a fixed routing, and wherein the p hard logic blocks are to provide h=n*p available hard data lanes, the data lanes having separate per-lane enables; and
placing a soft computing block comprising routable logic to communicatively couple the interconnect to a host platform and to provide for the interconnect k data lanes, wherein k<h;
wherein k−h lanes are to be disabled via the per-lane enables.
22. The method of claim 21 , further comprising disabling k h lanes.
23. The method of claim 21 , further comprising selectively mapping data lanes according to a switch mode.
24. The method of claim 21 , further comprising providing each lane a pseudo-random bit sequence for centering.
25. The method of claim 21 , further comprising distributing the k−h disabled lanes amongst the k data lanes.