FinFET devices and methods of forming the same

1. A FinFET device, comprising:

a substrate having at least one first fin and at least one second fin extending in a first direction;

a first gate extending in a second direction different from the first direction and across the at least one first fin,

a second gate extending in the second direction and across the at least one second fin, wherein ends of the first and second gates are faced to each other; and

a single spacer wall extending only in the first direction, located between the ends of the first and second gates and in physical contact with a gate dielectric material of each of the first and second gates,

wherein the single spacer wall traverses an NMOS region and a PMOS region, and

wherein the single spacer wall has a curved top portion and a vertical sidewall portion.

2. The FinFET device of claim 1 , wherein the single spacer wall comprises silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, copper oxide, nickel oxide, zinc oxide, lanthanum manganese oxide or lanthanum copper oxide.

3. The FinFET device of claim 1 , wherein the gate dielectric material comprises a dielectric material with a dielectric constant greater than 7.

4. The FinFET device of claim 1 , further comprising:

first spacers, disposed beside the first gate;

second spacers, disposed beside the second gate; and

third spacers, disposed beside the single spacer wall.

5. The FinFET device of claim 1 , wherein single spacer wall is made of a single insulating material.

6. The FinFET device of claim 1 , wherein the at least one first fin comprises multiple first fins and the first gate is across the multiple first fins, and the at least one second fin comprises multiple second fins and the second gate is across the multiple second fins.

7. A method of forming a FinFET device, comprising:

providing a substrate having at least one first fin and at least one second fin thereon and having an isolation layer formed to cover lower portions of the at least one first fin and the at least one second fin;

forming a stripe pattern between the at least one first fin and the at least one second fin;

forming two spacer walls beside the stripe pattern;

removing the stripe pattern and one of the spacer walls, wherein the remaining spacer wall extends only in one direction and traverses an NMOS region and a PMOS region, and the remaining spacer wall has a curved top portion and a vertical sidewall portion;

forming first and second dummy gates respectively across the at least one first fin and the at least one second fin, wherein the first and second dummy gates are arranged end to end and beside the remaining spacer wall;

forming a dielectric layer around the first and second dummy gates and the remaining spacer wall;

removing the first and second dummy gates to form first and second trenches in the dielectric layer; and

forming first and second gates in the first and second trenches.

8. The method of claim 7 , wherein the step of forming first and second dummy gates comprises:

forming a dummy layer around the at least one first, the at least one second fin and the remaining spacer wall;

forming mask patterns on the dummy layer; and

removing a portion of the dummy layer by using the mask patterns and the remaining spacer wall as an etching mask.

9. The method of claim 8 , the dummy layer comprises a silicon-containing material.

10. The method of claim 7 , further comprising, after the step of forming the first and second dummy gates and before the step of forming the dielectric layer,

forming first spacers beside the first dummy gate;

forming second spacers beside the second dummy gate; and

forming third spacers beside the remaining spacer wall.

11. The method of claim 7 , wherein each of the first and second gates comprises metal.

12. The method of claim 7 , wherein the at least one first fin comprises multiple first fins and the first gate is formed across the multiple first fins, and the at least one second fin comprises multiple second fins and the second gate is formed across the multiple second fins.

13. The method of claim 7 , wherein the spacer walls comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, copper oxide, nickel oxide, zinc oxide, lanthanum manganese oxide or lanthanum copper oxide or a combination thereof.

14. A FinFET device, comprising:

a substrate having first and second fins in a first region and third and fourth fins in a second region;

first and second gates respectively across the first and second fins, wherein ends of the first and second gates are faced to each other;

third and fourth gates respectively across the third and fourth fins, wherein ends of the third and fourth gates are faced to each other; and

a spacer wall located between the ends of the first and second gates and located between the ends of the third and fourth gates,

wherein the first region is an NMOS region and the second region is a PMOS region, and the spacer wall extends only in one direction and traverses the first and second regions, and

wherein the first and second gates comprise an N-type work function metal and the third and fourth gates comprise a P-type work function metal, and

wherein the spacer wall has a curved top portion and a vertical sidewall portion.

15. The FinFET device of claim 14 , further comprising a dielectric layer around the first to fourth gates and the spacer wall, wherein a material of the spacer wall is different from a material of the dielectric layer.

16. The FinFET device of claim 14 , wherein the spacer wall is in physical contact with a gate dielectric material of each of the first to fourth gates.

17. The FinFET device of claim 14 , wherein the spacer wall comprises a multi-layer structure.

18. The FinFET device of claim 14 , wherein the spacer wall is made of a single material.

19. The FinFET device of claim 14 , wherein

first spacers located beside the first gate;

second spacers located beside the third gate; and

third spacers located beside the spacer wall,

wherein a portion of the third spacers is disposed between the first gate and the third gate and is connected to a portion of the first spacers and a portion of the second spacers to form a U-shaped spacer.