Replacement III-V or germanium nanowires by unilateral confined epitaxial growth
A lateral epitaxial growth process is employed to facilitate the fabrication of a semiconductor structure including a stack of suspended III-V or germanium semiconductor nanowires that are substantially defect free. The lateral epitaxial growth process is unidirectional due to the use of masks to prevent epitaxial growth in both directions, which would create defects when the growth fronts merge. Stacked sacrificial material nanowires are first formed, then after masking and etching process to reveal a semiconductor seed layer, the sacrificial material nanowires are removed, and III-V compound semiconductor or germanium epitaxy is performed to fill the void previously occupied by the sacrificial material nanowires.
1. A semiconductor structure comprising:
an insulator structure located on a surface of a semiconductor material and containing a first end portion having a non-recessed surface, a middle portion having a recessed surface and a second end portion having said non-recessed surface;
a plurality of suspended and stacked III-V semiconductor nanowires located atop said first and second end portions of said insulator structure;
a functional gate structure surrounding a portion of each suspended and stacked III-V semiconductor nanowire located atop said first and second end portions of said insulator structure;
a source/drain semiconductor material structure located on each side of each functional gate structure and directly contacting a sidewall of each suspended and stacked III-V semiconductor nanowire; and
a barrier material extending upwards from said recessed surface of said insulator structure and separating one of said source/drain semiconductor material structures of one of said functional gate structures from another of said source/drain semiconductor material structures of another of said functional gate structures.
2. The semiconductor structure of claim 1 , wherein a topmost surface of said barrier material is coplanar with a topmost surface of a topmost functional gate structure.
3. The semiconductor structure of claim 1 , wherein at least one of said source/drain semiconductor material structures has a bottommost surface that directly contacts a semiconductor surface of said semiconductor material.
4. The semiconductor structure of claim 3 , wherein said semiconductor surface of said semiconductor material is a recessed surface that is located beneath a bottommost surface of said insulator structure.
5. The semiconductor structure of claim 1 , wherein a dielectric spacer is located adjacent each functional gate structure, wherein an outermost sidewall of said dielectric spacer is vertically aligned with an outermost surface of each of said suspended and stacked III-V semiconductor nanowires.
6. The semiconductor structure of claim 1 , further comprising a middle-of-the-line (MOL) dielectric material located atop each source/drain semiconductor material structure, wherein said MOL dielectric material has a topmost surface that is coplanar with a topmost surface of each topmost functional gate structure.
7. The semiconductor structure of claim 6 , further comprising a barrier liner located at least between said MOL dielectric material and each source/drain semiconductor material structure.
8. The semiconductor structure of claim 1 , wherein said suspended and stacked III-V semiconductor nanowires have an epitaxially relationship with said semiconductor material.
9. The semiconductor structure of claim 1 , wherein each suspended and stacked III-V semiconductor nanowires located atop said first and second end portions of said insulator structure has outermost sidewalls that are vertically aligned to each other.
10. The semiconductor structure of claim 1 , wherein said barrier material has a height that is greater than a height of each of said source/drain semiconductor material structures.
11. A semiconductor structure comprising:
an insulator structure located on a surface of a semiconductor material and containing a first end portion having a non-recessed surface, a middle portion having a recessed surface and a second end portion having said non-recessed surface;
a plurality of suspended and stacked germanium semiconductor nanowires located atop said first and second end portions of said insulator structure;
a functional gate structure surrounding a portion of each suspended and stacked germanium semiconductor nanowire located atop said first and second end portions of said insulator structure;
a source/drain semiconductor material structure located on each side of said functional gate structure and directly contacting a sidewall of each suspended and stacked germanium semiconductor nanowire; and
a barrier material extending upwards from said recessed surface of each insulator structure and separating one of said source/drain semiconductor material structures of one of said functional gate structures from another of said source/drain semiconductor material structures of another of said functional gate structures.
12. The semiconductor structure of claim 11 , wherein a topmost surface of said barrier material is coplanar with a topmost surface of a topmost functional gate structure.
13. The semiconductor structure of claim 11 , wherein at least one of said source/drain semiconductor material structures has a bottommost surface that directly contacts a semiconductor surface of said semiconductor material.
14. The semiconductor structure of claim 13 , wherein said semiconductor surface of said semiconductor material is a recessed surface that is located beneath a bottommost surface of said insulator structure.
15. The semiconductor structure of claim 11 , wherein a dielectric spacer is located adjacent each functional gate structure, wherein an outermost sidewall of said dielectric spacer is vertically aligned with an outermost surface of each of said suspended and stacked germanium semiconductor nanowires.
16. The semiconductor structure of claim 11 , further comprising a middle-of-the-line (MOL) dielectric material located atop each source/drain semiconductor material structure, wherein said MOL dielectric material has a topmost surface that is coplanar with a topmost surface of each topmost functional gate structure.
17. The semiconductor structure of claim 16 , further comprising a barrier liner located at least between said MOL dielectric material and each source/drain semiconductor material structure.
18. The semiconductor structure of claim 11 , wherein said suspended and stacked germanium semiconductor nanowires have an epitaxial relationship with said semiconductor material.
19. The semiconductor structure of claim 11 , wherein each suspended and stacked germanium semiconductor nanowires located atop said first and second end portions of said insulator structure has outermost sidewalls that are vertically aligned to each other.
20. The semiconductor structure of claim 11 , wherein said barrier material has a height that is greater than a height of each of said source/drain semiconductor material structures.