Method, apparatus, and system for plugin mechanism of computer extension bus
Method, apparatus, and system of detecting a hot-plug event. The hot-plug event detection may be done in-band or out-of-band. The in-band detection is performed by a state machine and the out-of-band detection is performed by a logic. A circuitry is to detect a hot-plug event when inserting or removing a device from an extension bus of the plurality of extension bus slots. The circuit is to generate a hot-plug message to notify the hot-plug event. The circuitry including the state machine, the logic and a register to provide at least two bits to mask at least two states of the state machine.
1. An apparatus comprising:
a processor;
a bus operably coupled to the processor;
an extension bus slot operably coupled to the bus; and
a circuitry to detect a hot-plug event when inserting or removing a device from the extension bus slot, and to generate a hot-plug message to notify of an occurrence of the hot-plug event, the circuitry comprising:
a state machine to detect the hot-plug event; and
a register to provide at least two bits to mask at least two states of the state machine.
2. The apparatus of claim 1 , wherein the register is to select between an in-band hot-plug detection and an out-of-band hot-plug detection.
3. The apparatus of claim 1 , wherein the register is to select both an in-band hot-plug detection and an out-of-band hot-plug detection.
4. The apparatus of claim 1 , wherein the extension bus slot comprises a Peripheral Component Interconnect express (PCIe) slot.
5. The apparatus of claim 1 , wherein the device comprises a Peripheral Component Interconnect express (PCIe) device.
6. The apparatus of claim 1 , wherein the state machine comprises a Peripheral Component Interconnect express (PCIe) link training and status state machine (LTSSM), the PCIe LTSSM is to be in at least one of a Detect state, a Polling state or a Configuration state.
7. The apparatus of claim 6 , wherein the register is to mask a Polling state indication and a Configuration state indication of the PCIe LTSSM.
8. The apparatus of claim 1 comprising:
a virtual port pin (VPP) logic to provide an out of band hot-plug event detection indication.
9. A method comprising:
selecting between an in-band hot-plug detection mechanism, an out-of-band hot-plug detection mechanism, or both the in-band hot-plug detection and the out-of-band hot-plug detection;
detecting a hot-plug event when inserting or removing a device from an extension bus slot, wherein according to the in-band hot-plug detection mechanism, detecting the hot-plug event is by a state machine having at least three states and by masking at least two states of the state machine; and
generating a hot-plug event message to notify of an occurrence of the hot-plug event.
10. The method of claim 9 , wherein the extension bus slot comprises a Peripheral Component Interconnect express (PCIe) slot.
11. The method of claim 9 , wherein the device comprises a Peripheral Component Interconnect express (PCIe) device.
12. The method of claim 9 , wherein the state machine comprises a Peripheral Component Interconnect express (PCIe) link training and status state machine (LTSSM), the PCIe LTSSM is to be in at least one of a Detect state, a Polling state or a Configuration state.
13. The method of claim 12 , wherein masking comprises:
masking a Polling state indication or a Configuration state indication of the PCIe LTSSM.
14. The method of claim 9 , wherein according to the out-of-band detection mechanism, detecting the hot-plug event is by a virtual port pin (VPP) logic and by writing a detection of a hot-plug event status into a register.
15. A system comprising:
an apparatus comprising:
a processor;
a plurality of buses operably coupled to the processor;
a plurality of extension bus slots operably coupled to the plurality of buses; and
a circuitry to detect a hot-plug event when inserting or removing a device from an extension bus slot of the plurality of extension bus slots, and to generate a hot-plug message to notify of an occurrence of the hot-plug event, the circuitry comprising:
a state machine to detect the hot-plug event; and
a register to provide at least two bits to mask at least two states of the state machine.
16. The system of claim 15 , wherein the register is to select between an in-band hot-plug detection and an out-of-band hot-plug detection.
17. The system of claim 15 , wherein the register is to select both an in-band hot-plug detection and an out-of-band hot-plug detection.
18. The system of claim 15 , wherein the extension bus slot comprises a Peripheral Component Interconnect express (PCIe) slot.
19. The system of claim 15 , wherein the device comprises a Peripheral Component Interconnect express (PCIe) device.
20. The system of claim 15 , wherein the state machine comprises a Peripheral Component Interconnect express (PCIe) link training and status state machine (LTSSM), the PCIe LTSSM is to be in at least one of a Detect state, a Polling state or a Configuration state.
21. The system of claim 20 , wherein the register is to mask a Polling state indication and a Configuration state indication of the PCIe LTSSM.
22. The system of claim 15 comprising:
a virtual port pin (VPP) logic to provide an out of band hot-plug event detection indication.