Barrier layer above anti-punch through (APT) implant region to improve mobility of channel region of fin field effect transistor (FinFET) device structure
A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from the substrate. The FinFET device structure also includes an anti-punch through implant (APT) region formed in the fin structure and a barrier layer formed on the APT region. The barrier layer has a middle portion and a peripheral portion, and the middle portion is higher than the peripheral portion. The FinFET device structure further includes an epitaxial layer formed on the barrier layer.
1. A fin field effect transistor (FinFET) device structure, comprising:
a substrate;
a fin structure extending from the substrate;
an anti-punch through implant (APT) region formed in the fin structure;
a barrier layer formed on the APT region, wherein the barrier layer has a width in a horizontal direction, and the width gradually tapers from a bottom of the barrier layer to a top of the barrier layer; and
an epitaxial layer formed on the barrier layer.
2. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the barrier layer has convex structure.
3. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the barrier layer comprises silicon carbide (SiC) or silicon germanium carbide (SiGeC).
4. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the barrier layer is epitaxially grown along the (111) plane.
5. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , further comprising:
an isolation structure formed on the substrate, wherein the fin structure is embedded in the isolation structure, and the APT region is below a top surface of the isolation structure.
6. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , further comprising:
a liner formed on the sidewalls of the fin structure.
7. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the epitaxial layer comprises silicon germanium (SiGe), germanium (Ge) or combinations thereof.
8. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the barrier layer has a middle portion having a raised height over a top surface of the APT region, and the raised height is in a range from about 5 nm to about 10 nm.
9. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the entire barrier layer is higher than a top surface of the first APT region.
10. A fin field effect transistor (FinFET) device structure, comprising:
a substrate;
a first fin structure and a second fin structure formed on the substrate;
a first anti-punch through implant (APT) region formed in the first fin structure;
a barrier layer formed on the first APT region, wherein the barrier layer has a convex structure, wherein the barrier layer has a horizontal width which gradually tapers from a bottom to a top of the barrier layer; and
an epitaxial layer formed on the barrier layer;
a second APT region formed in the second fin structure; and
an isolation structure formed on the substrate, wherein a top surface of the first APT region is below a top surface of the isolation structure.
11. The fin field effect transistor (FinFET) device structure as claimed in claim 10 , wherein the barrier layer has a middle portion and a peripheral portion, and the middle portion is higher than the peripheral portion.
12. The fin field effect transistor (FinFET) device structure as claimed in claim 10 , wherein the first fin structure is configured to form a p-type FinFET, and the second fin structure is configured to form an n-type FinFET.
13. The fin field effect transistor (FinFET) device structure as claimed in claim 10 , wherein the epitaxial layer comprises silicon germanium (SiGe), germanium (Ge) or combinations thereof.
14. The fin field effect transistor (FinFET) device structure as claimed in claim 10 , wherein the second APT region is higher than the top surface of the isolation structure.
15. The fin field effect transistor (FinFET) device structure as claimed in claim 10 , wherein the barrier layer is epitaxially grown along the (111) plane.
16. The fin field effect transistor (FinFET) device structure as claimed in claim 10 , further comprising:
a gate dielectric layer formed on the epitaxial layer; and
a gate electrode layer formed on the gate dielectric layer.
17. The fin field effect transistor (FinFET) device structure as claimed in claim 10 , wherein the entire barrier layer is higher than a top surface of the first APT region.
18. A fin field effect transistor (FinFET) device structure, comprising:
a substrate;
a first fin structure and a second fin structure extending from the substrate;
an isolation structure formed over the substrate, wherein the first fin structure and the second fin structure are embedded in the isolation structure;
a first anti-punch through implant (APT) region formed in the first fin structure;
a barrier layer formed on the first APT region, wherein the barrier layer has a convex cross-sectional profile with two outer-most points which are level with a top surface of the isolation structure;
an epitaxial structure formed over the barrier layer, wherein the epitaxial structure has a curved bottom surface; and
a second APT region formed over the second fin structure, wherein a top surface of the second APT region is level with a top surface of the epitaxial structure.
19. The fin field effect transistor (FinFET) device structure as claimed in claim 18 , wherein the first APT region is below a top surface of the isolation structure, and the second APT region is higher than the top surface of the isolation structure.