3D semiconductor device and system
A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and the third transistor is controlled by a third control line, where the second transistor is overlaying the first transistor and the second transistor is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and the third control line, and where the second transistor and the third transistor are self-aligned.
1. A 3D integrated circuit device, comprising:
a first transistor;
a second transistor; and
a third transistor,
wherein said third transistor is overlaying said second transistor and said third transistor is controlled by a third control line,
wherein said second transistor is overlaying said first transistor and said second transistor is controlled by a second control line,
wherein said first transistor is part of a control circuit controlling said second control line and said third control line,
wherein said second transistor and said third transistor are self-aligned.
2. The device according to claim 1 ,
wherein said second transistor is aligned to said first transistor with less than 100 nm and greater than 5 nm misalignment.
3. The device according to claim 1 , further comprising:
a third memory cell comprising said third transistor;
a second memory cell comprising said second transistor; and
memory periphery circuits comprising said first transistor,
wherein said memory periphery circuits control at least said third memory cell and second memory cell.
4. The device according to claim 1 ,
wherein said second transistor is connected to said third transistor with an ohmic connection.
5. The device according to claim 1 ,
wherein said second transistor is a junction-less transistor.
6. The device according to claim 1 ,
wherein said second transistor comprises a schottky barrier.
7. The device according to claim 1 ,
wherein said second transistor comprises a second source and a second drain,
wherein said third transistor comprises a third source and a third drain,
wherein said second source is connected to said third source and said second drain is connected to said third drain, each with an ohmic connection.
8. A 3D integrated circuit device, comprising:
a first transistor;
a second transistor; and
a third transistor,
wherein said third transistor is overlaying said second transistor and said third transistor is controlled by a third control line,
wherein said second transistor is overlaying said first transistor and said second transistor is controlled by a second control line,
wherein said second transistor comprises a schottky barrier, and
wherein said second transistor and said third transistor are self-aligned.
9. The device according to claim 8 ,
wherein said second transistor is aligned to said first transistor with less than 100 nm and greater than 5 nm misalignment.
10. The device according to claim 8 , further comprising:
a third memory cell comprising said third transistor;
a second memory cell comprising said second transistor; and
memory periphery circuits comprising said first transistor,
wherein said memory periphery circuits control at least said third memory cell and second memory cell.
11. The device according to claim 8 ,
wherein said second transistor is connected to said third transistor with an ohmic connection.
12. The device according to claim 8 ,
wherein said second transistor is a junction-less transistor.
13. The device according to claim 8 ,
wherein said first transistor is part of a control circuit controlling said second control line and said third control line.
14. The device according to claim 8 ,
wherein said second transistor comprises a second source and a second drain,
wherein said third transistor comprises a third source and a third drain,
wherein said second source is connected to said third source and said second drain is connected to said third drain, each with an ohmic connection.
15. A 3D integrated circuit device, comprising:
a first transistor;
a first memory cell comprising a second transistor; and
a second memory cell comprising a third transistor,
wherein said third transistor is overlaying said second transistor and said second transistor is overlaying said first transistor,
wherein said first transistor is part of a control circuit controlling said first memory cell and second memory cell,
wherein said second transistor is self-aligned to said third transistor, and
wherein said second transistor is connected to said third transistor with an ohmic connection.
16. The device according to claim 15 ,
wherein said first transistor, said second transistor and said third transistor are aligned to each other with less than 100 nm and greater than 5 nm misalignment.
17. The device according to claim 15 , further comprising:
memory periphery circuits comprising said first transistor,
wherein said memory periphery circuits control at least said first memory cell and second memory cell.
18. The device according to claim 15 ,
wherein said second transistor is a junction-less transistor.
19. The device according to claim 15 ,
wherein said second transistor comprises a schottky barrier.
20. The device according to claim 15 ,
wherein said second transistor comprises a second source and a second drain,
wherein said third transistor comprises a third source and a third drain,
wherein said second source is connected to said third source and said second drain is connected to said third drain, each with an ohmic connection.