Semiconductor devices and fabricating methods thereof
Provided are semiconductor devices and fabricating methods thereof. The semiconductor device includes a field insulating layer formed in a substrate, an interlayer dielectric layer formed on the field insulating layer and including a trench exposing at least a portion of the field insulating layer, a deposition insulating layer formed in the trench to be disposed on the field insulating layer, a gate insulating layer formed the trench to be disposed on the deposition insulating layer, and a metal gate formed the trench on the gate insulating layer.
1. A semiconductor device comprising:
a fin protruded from a substrate;
a field insulation layer disposed on the substrate;
a first gate disposed on the fin; and
a source/drain region between the first gate and the field insulation layer; and
a second gate disposed on the field insulation layer,
wherein a first distance between a bottom surface of the source/drain region and a top surface of the source/drain region is greater than a second distance between a top surface of the field insulation layer and a top surface of the fin, and the second distance is greater than a third distance between a top surface of the source/drain region to a top surface of the first gate.
2. The semiconductor device of claim 1 , wherein the first gate includes a metal gate pattern and a work function control film covering at least a bottom and both opposite sides of the metal gate pattern.
3. The semiconductor device of claim 2 , further comprising a gate insulating layer disposed between the work function control film and the top surface of the fin.
4. The semiconductor device of claim 1 , wherein the substrate is a group III-V substrate.
5. The semiconductor device of claim 1 , wherein the source/drain region includes SiGe.
6. The semiconductor device of claim 1 , wherein the first gate is a normal gate and the second gate is a dummy gate.
7. A semiconductor device comprising:
a fin protruded from a substrate;
a field insulation layer disposed on the substrate;
a first gate disposed on the fin;
a source/drain region between the first gate and the field insulation layer; and
a second gate disposed on the field insulation layer,
wherein a first distance between a bottom surface of the source/drain region and a top surface of the source/drain region is greater than a second distance between the bottom surface of the source/drain region and a top surface of the fin, and the second distance is greater than a third distance between a bottom surface of the first gate to a top surface of the first gate.
8. The semiconductor device of claim 7 , wherein the first gate includes a metal gate pattern and a work function control film covering at least a bottom and both opposite sides of the metal gate pattern.
9. The semiconductor device of claim 8 , further comprising a gate insulating layer disposed between the work function control film and the top surface of the fin.
10. The semiconductor device of claim 7 , wherein the substrate is a group III-V substrate.
11. The semiconductor device of claim 7 , wherein the source/drain region includes SiGe.
12. The semiconductor device of claim 7 , wherein the first gate is a normal gate and the second gate is a dummy gate.