IP Library › Granted Patent US 9,954,113
Granted Patent B2
US 9,954,113 · App. 15/017,831 · Granted Apr 24, 2018

Transistor including oxide semiconductor, semiconductor device including the transistor, and electronic device including the transistor

Inventors: Akihisa Shimomura (Tochigi, JP); Satoru Okamoto (Kanagawa, JP); Yutaka Okazaki (Kanagawa, JP); Yoshinobu Asami (Kanagawa, JP); Hiroaki Honda (Kanagawa, JP); Takuya Tsurume (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/7869H01L27/1225H01L29/0688H01L29/42384H01L29/78696
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Quick Facts
Patent No.
US 9,954,113
App. No.
15/017,831
Granted
Apr 24, 2018
Kind
B2
Abstract

A transistor with favorable electrical characteristics is provided. A transistor with stable electrical characteristics is provided. A semiconductor device having a high degree of integration is provided. Side surfaces of an oxide semiconductor layer in which a channel is formed are covered with an oxide semiconductor layer, whereby impurity diffusion from the side surfaces of the oxide semiconductor into the inside can be prevented. A gate electrode is formed by a damascene process, whereby transistors can be miniaturized and formed at a high density.

Claims (62)

1. A transistor comprising:

a first oxide semiconductor layer, a second oxide semiconductor layer and a third oxide semiconductor layer;

a first electrode, a second electrode, and a third electrode; and

a first insulating layer and a second insulating layer,

wherein the first oxide semiconductor layer comprises a first region, a second region, and a third region between the first region and the second region,

wherein the first electrode is over the first region,

wherein the second electrode is over the second region,

wherein the first insulating layer is over the first electrode and the second electrode with the second oxide semiconductor layer therebetween,

wherein the second oxide semiconductor layer comprises a first opening,

wherein the first insulating layer comprises a second opening,

wherein the first opening and the second opening each overlap with the third region,

wherein the third electrode is over the third region with the third oxide semiconductor layer and the second insulating layer therebetween,

wherein the second oxide semiconductor layer covers a first side surface, a second side surface, the first region, and the second region of the first oxide semiconductor layer,

wherein the third oxide semiconductor layer covers third side surfaces and the third region of the first oxide semiconductor layer,

wherein the third oxide semiconductor layer, the second insulating layer, and the third electrode are provided inside the second opening, and

wherein a top surface of each of the third oxide semiconductor layer, the second insulating layer, and the third electrode are aligned with each other.

2. The transistor according to claim 1 ,

wherein the first region comprises the first side surface,

wherein the second region comprises the second side surface, and

wherein the third region comprises the third side surfaces.

3. The transistor according to claim 1 , wherein each of the second oxide semiconductor layer and the third oxide semiconductor layer has a layered crystal structure substantially parallel to the first side surface, the second side surface, and the third side surfaces of the first oxide semiconductor layer.

4. The transistor according to claim 1 , wherein side surfaces of the third electrode are surrounded by the first insulating layer.

5. The transistor according to claim 1 , wherein the second oxide semiconductor layer is in contact with the first side surface and the second side surface of the first oxide semiconductor layer.

6. The transistor according to claim 1 , wherein the third oxide semiconductor layer is in contact with the third side surfaces of the first oxide semiconductor layer.

7. The transistor according to claim 1 , wherein a channel is formed in the third region.

8. The transistor according to claim 1 , wherein the first oxide semiconductor layer comprises at least one of In and Zn.

9. The transistor according to claim 1 , wherein the second oxide semiconductor layer and the third oxide semiconductor layer comprise at least one of metal elements contained in the first oxide semiconductor layer.

10. A semiconductor device comprising:

the transistor according to claim 1 ; and

a capacitor or a resistor.

11. An electronic device comprising:

the transistor according to claim 1 ; and

at least one of an antenna, a battery, an operation switch, a microphone, and a speaker.

12. The transistor according to claim 1 , wherein a top surface of the first insulating layer is aligned with the top surface of each of the third oxide semiconductor layer, the second insulating layer, and the third electrode.

13. The transistor according to claim 1 , wherein the first opening and the second opening are continuous.

14. A transistor comprising:

a first oxide semiconductor layer;

a first electrode and a second electrode over the first oxide semiconductor layer;

a second oxide semiconductor layer over the first electrode and the second electrode, the second oxide semiconductor layer comprising a first opening;

a first insulating layer over the second oxide semiconductor layer, the first insulating layer comprising a second opening;

a third oxide semiconductor layer in the first opening and the second opening;

a second insulating layer over the third oxide semiconductor layer; and

a third electrode over the third oxide semiconductor layer,

wherein the second oxide semiconductor layer covers first side surfaces of the first oxide semiconductor layer in a channel length direction of the transistor,

wherein the third oxide semiconductor layer covers second side surfaces of the first oxide semiconductor layer in a channel width direction of the transistor,

wherein the third oxide semiconductor layer, the second insulating layer, and the third electrode are provided inside the second opening, and

wherein a top surface of each of the third oxide semiconductor layer, the second insulating layer, and the third electrode are aligned with each other.

15. The transistor according to claim 14 ,

wherein the first opening overlaps with the second opening, and

wherein the third oxide semiconductor layer is in contact with the first oxide semiconductor layer in the first opening and the second opening.

16. The transistor according to claim 14 , wherein each of the second oxide semiconductor layer and the third oxide semiconductor layer has a layered crystal structure substantially parallel to the first side surfaces and the second side surfaces of the first oxide semiconductor layer.

17. The transistor according to claim 14 , wherein side surfaces of the third electrode are surrounded by the first insulating layer.

18. The transistor according to claim 14 , wherein the second oxide semiconductor layer is in contact with the first side surfaces of the first oxide semiconductor layer.

19. The transistor according to claim 14 , wherein the third oxide semiconductor layer is in contact with the second side surfaces of the first oxide semiconductor layer.

20. The transistor according to claim 14 , wherein a channel is formed in the first oxide semiconductor layer.

21. The transistor according to claim 14 , wherein the first oxide semiconductor layer comprises at least one of In and Zn.

22. The transistor according to claim 14 , wherein the second oxide semiconductor layer and the third oxide semiconductor layer comprise at least one of metal elements contained in the first oxide semiconductor layer.

23. A semiconductor device comprising:

the transistor according to claim 14 ; and

a capacitor or a resistor.

24. The transistor according to claim 14 , wherein a top surface of the first insulating layer is aligned with the top surface of each of the third oxide semiconductor layer, the second insulating layer, and the third electrode.

25. The transistor according to claim 14 , wherein the first opening and the second opening are continuous.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 28, 2016
From: SHIMOMURA, AKIHISA; OKAMOTO, SATORU; OKAZAKI, YUTAKA; ASAMI, YOSHINOBU; HONDA, HIROAKI; TSURUME, TAKUYA
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 038114/0888 →
Priority Claims (1)
JP 2015-023137 · Feb 9, 2015 · national
Continuity (1)
Related Publication 20160233340A1 · Aug 11, 2016