IP Library Granted Patent US 9,954,450
Granted Patent B2
US 9,954,450 · App. 15/456,229 · Granted Apr 24, 2018

Control circuit, control method and primary-controlled flyback converter using the same

Inventors: Huiqiang Chen (Hangzhou, CN); Jianxin Wang (Hangzhou, CN)
Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
H02M3/33515H02M1/08H02M3/33523H02M2001/0009
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Quick Facts
Patent No.
US 9,954,450
App. No.
15/456,229
Granted
Apr 24, 2018
Kind
B2
Abstract

In one embodiment, a control circuit configured to control a power stage circuit of a primary-controlled flyback converter, can include: (i) a current sense circuit that generates a current sense signal by sampling a primary current; (ii) a voltage sense circuit that generates a voltage sense signal by sampling an auxiliary voltage after a blanking time has elapsed; (iii) a control signal generator that generates a switch control signal according to the voltage sense signal and the current sense signal; and (iv) the switch control signal being configured to control a power switch of the power stage circuit, where the switch control signal is active during a constant on time.

Claims (41)

1. A control circuit configured to control a power stage circuit of a flyback converter, the control circuit comprising:

e) a control signal generator configured to generate a switch control signal to control the operation of said power stage circuit;

f) said power stage circuit being controlled by said switch control signal to operate in a peak current control mode when a supply voltage of said power stage circuit is less than a predetermined value; and

g) said power stage circuit being controlled by said switch control signal to operate in a constant time control mode when said supply voltage is greater than said predetermined value.

2. A primary-controlled flyback converter, comprising the control circuit of claim 1 , and further comprising said power stage circuit.

3. The control circuit of claim 1 , further comprising a set signal generation circuit configured to generate a set signal by detecting valley information of a voltage across a primary winding of said power stage circuit after a blanking time adjusted in accordance with a primary current of said power stage circuit.

4. The control circuit of claim 1 , further comprising a voltage sensing circuit having an auxiliary winding coupled to a primary winding of said power stage circuit, and being configured to generate a voltage sensing signal.

5. The control circuit of claim 3 , further comprising a blanking circuit configured to generate said blanking time in accordance with a peak value of said primary current.

6. The control circuit of claim 3 , further comprising a reset signal generation circuit configured to generate a reset signal in accordance with a constant time signal when said power stage circuit is operated in said constant time control mode, and to generate a peak current signal when said power stage circuit is operated in said peak current control mode.

7. The control circuit of claim 5 , wherein said blanking time is a linear function of a peak of said current sense signal when said peak is greater than a first value and less than a second value.

8. The control circuit of claim 5 , wherein said voltage sense circuit comprises

a blanking circuit configured to generate said blanking time as a first constant time when said peak of said current sense signal is less than said first value, and to generate said blanking time as a second constant time when said peak of said current sense signal is greater than said second value.

9. The control circuit of claim 8 , wherein said blanking circuit comprises:

a) a blanking threshold generator configured to generate a blanking threshold according to said peak of said current sense signal, said first value, and said second value; and

b) a blanking timing circuit configured to generate said blanking signal according to said blanking threshold.

10. The control circuit of claim 6 , wherein said control signal generator comprises

c) a logic circuit configured to activate said switch control signal in response to said set signal being activated, and to deactivate said switch control signal in response to said reset signal being activated.

11. The control circuit of claim 6 , wherein said reset signal generator comprises a time circuit configured to generate a constant on time in accordance with an error between an output voltage of said power stage circuit and a predetermined voltage.

12. The control circuit of claim 11 , wherein said reset signal generator further comprises:

b) a comparator configured to generate a comparison result according to said primary current and a current threshold; and

c) a reset logic circuit configured to generate said reset signal according to said timing signal and said comparison result.

13. A control circuit configured to control a power stage circuit of a flyback converter, the control circuit comprising:

a) a current sense circuit configured to generate a current sense signal by sampling a primary current;

b) a voltage sense circuit configured to generate a voltage sense signal by sampling an auxiliary voltage after a blanking time, wherein said blanking time is adjusted in accordance with a peak value of said current sense signal; and

c) a control signal generator configured to generate a switch control signal

d) that is configured to control a power switch of said power stage circuit.

14. The control circuit of claim 13 , wherein said voltage sense circuit comprises:

a) a blanking circuit configured to generate said blanking time as a first constant time when said peak of said current sense signal is less than said first value, and to generate said blanking time as a second constant time when said peak of said current sense signal is greater than said second value; and

b) a sampling circuit configured to sample a voltage according to said blanking time.

15. The control circuit of claim 14 , wherein said blanking circuit comprises:

a) a blanking threshold generator configured to generate a blanking threshold according to said peak of said current sense signal, said first value, and said second value; and

b) a blanking timing circuit configured to generate a blanking signal according to said blanking threshold.

16. A method of controlling a power stage circuit of a flyback converter, the method comprising:

e) generating, by a control signal generator, a switch control signal for controlling the operation of said power stage circuit;

f) controlling, by said switch control signal, said power stage circuit to operate in a peak current control mode when a supply voltage of said power stage circuit is less than a predetermined value; and

g) controlling, by said switch control signal, said power stage circuit to operate in a constant time control mode when said supply voltage is greater than said predetermined value.

17. The method of claim 16 , wherein said controlling said power stage circuit comprises:

a) turning on a power switch of said power stage circuit when a voltage sense signal representing a voltage across a primary winding drops to a valley value; and

b) turning off said power switch when at least one of: said switch control signal remains active for a constant on time and a current sense signal representing a current of said primary winding reaches a current threshold.

18. The method of claim 17 , wherein said valley value is detected after a blanking time that is adjusted in accordance with a primary current of said power stage circuit.

19. The method of claim 18 , wherein said blanking time is a linear function of a peak of said current sense signal when said peak is greater than a first value and less than a second value.

Priority Claims (2)
CN 2014 1 0170914 · Apr 25, 2014 · national
CN 2015 1 0180544 · Apr 16, 2015 · national
Continuity (2)
Continuation 14695337 · Apr 24, 2015
Related Publication 20170187295A1 · Jun 29, 2017