IP Library › Granted Patent US 9,960,076
Granted Patent B2
US 9,960,076 · App. 15/229,985 · Granted May 1, 2018

Devices with backside metal structures and methods of formation thereof

Inventors: Oliver Hellmund (Neubiberg, DE); Ingo Muri (Villach, AT); Johannes Baumgartl (Riegersdorf, AT); Iris Moder (Villach, AT); Thomas Christian Neidhart (Klagenfurt, AT); Hans-Joachim Schulze (Taufkirchen, DE)
Assignee: Infineon Technologies AG
H01L21/76248H01L21/28H01L21/30608H01L21/30625H01L21/31111H01L21/76272H01L21/76283H01L29/4236H01L29/66666H01L29/7827H01L21/31053
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Quick Facts
Patent No.
US 9,960,076
App. No.
15/229,985
Granted
May 1, 2018
Kind
B2
Abstract

A method of fabricating a semiconductor device includes forming trenches filled with a sacrificial material. The trenches extend into a semiconductor substrate from a first side. An epitaxial layer is formed over the first side of the semiconductor substrate and the trenches. From a second side of the semiconductor substrate opposite to the first side, the sacrificial material in the trenches is removed. The trenches are filled with a conductive material.

Claims (63)

1. A method of fabricating a semiconductor device, the method comprising:

forming trenches filled with a sacrificial material, the trenches extending into a semiconductor substrate from a first side;

forming an epitaxial layer over the first side of the semiconductor substrate and the trenches;

from a second side of the semiconductor substrate opposite to the first side, removing the sacrificial material in the trenches; and

filling the trenches with a conductive material, wherein a top portion of each of the trenches is filled with the epitaxial layer and a bottom portion of each of the trenches is filled with the conductive material.

2. The method of claim 1 , further comprising forming a device region in the epitaxial layer.

3. The method of claim 2 , wherein the device region comprises a source region of a transistor.

4. The method of claim 1 , further comprising thinning the semiconductor substrate from the second side to expose the sacrificial material.

5. The method of claim 4 , wherein a surface of the sacrificial material that is exposed is substantially planar.

6. The method of claim 4 , wherein a vertical cross section of a surface of the sacrificial material that is exposed has a v-shape.

7. The method of claim 4 , wherein thinning the semiconductor substrate comprises a chemical mechanical planarization process.

8. The method of claim 4 , wherein thinning the semiconductor substrate comprises an anisotropic wet etching process.

9. The method of claim 8 , wherein the anisotropic wet etching process comprises a tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH) etchant.

10. The method of claim 1 , wherein the each of the trenches comprise a plurality of sidewalls and a bottom surface, and wherein forming the trenches comprises:

forming a liner over a major surface of the semiconductor substrate, the sidewalls of the trenches, and the bottom surface of each of the trenches; and

forming a fill material over the liner.

11. The method of claim 1 , wherein forming the trenches comprises:

forming the sacrificial material within the trenches, the sacrificial material contacting the semiconductor substrate.

12. The method of claim 1 , wherein the sacrificial material comprises:

a void region in a central region of the sacrificial material, wherein the void region is surrounded entirely by the sacrificial material.

13. The method of claim 1 , wherein the sacrificial material comprises at least one of a thermal oxide, a CVD oxide, a nitride, amorphous carbon, and graphite, wherein the conductive material comprises at least one of a metal, a ternary carbide, and a ternary nitride.

14. The method of claim 1 , wherein the semiconductor device is a vertical device, wherein the conductive material forms a back side contact to the semiconductor device.

15. The method of claim 1 , further comprising:

etching the sacrificial material to expose a top surface of the semiconductor substrate at the first side, the etching removing portions of the sacrificial material from top portions of the trenches.

16. The method of claim 1 , wherein forming the epitaxial layer comprises growing the epitaxial layer starting from the first side of the semiconductor substrate, the epitaxial layer laterally growing over the trenches.

17. The method of claim 1 , wherein forming the trenches comprises:

forming the trenches in the semiconductor substrate from the first side;

oxidizing the trenches to form an oxide liner; and

depositing a fill material using a chemical vapor deposition process, wherein the sacrificial material comprises the oxide liner and the fill material.

18. The method of claim 2 , wherein the device region comprises a trench gate device, and wherein a trench gate of the trench gate device is disposed over one of the trenches.

19. The method of claim 3 , wherein the transistor is a vertical MOSFET, and wherein the conductive material forms a back side contact to the vertical MOSFET.

20. A method of fabricating a semiconductor device, the method comprising:

forming trenches comprising sidewalls extending into a semiconductor substrate from a first side;

oxidizing the trenches to form a first region of a sacrificial material;

depositing a fill material over the first region and in the trenches to form a second region of the sacrificial material;

etching the sacrificial material to expose a top surface of the semiconductor substrate at the first side, the etching exposing regions of the sidewalls at top portions of the trenches;

from a second side of the semiconductor substrate opposite to the first side, removing the sacrificial material in the trenches; and

filling the trenches with a conductive material.

21. The method of claim 20 , wherein each of the trenches comprises a bottom surface, and wherein oxidizing the trenches comprises forming an oxide liner on the sidewalls and the bottom surface of each of the trenches.

22. The method of claim 20 , wherein depositing the fill material comprises depositing the fill material using a chemical vapor deposition process.

23. The method of claim 20 , further comprising:

forming an epitaxial layer over the first side of the semiconductor substrate and the trenches; and

forming a device region in the epitaxial layer.

24. A method of fabricating a semiconductor device, the method comprising:

forming trenches extending into a semiconductor substrate from a first side;

filling the trenches with a sacrificial material;

forming a device region comprising the semiconductor device over the trenches at the first side;

from a second side of the semiconductor substrate opposite the first side, removing the sacrificial material in the trenches; and

filling the trenches with a conductive material, wherein the semiconductor device is a vertical power semiconductor device, and wherein the conductive material makes direct Ohmic contact with the vertical power semiconductor device.

25. The method of claim 24 , wherein the vertical power semiconductor device is a diode.

26. The method of claim 24 , wherein the vertical power semiconductor device is a transistor.

27. A method of fabricating a semiconductor device, the method comprising:

forming trenches filled with a sacrificial material, the trenches extending into a semiconductor substrate from a first side;

forming a first epitaxial layer over the first side of the semiconductor substrate and the trenches;

forming a second epitaxial layer over the first epitaxial layer;

from a second side of the semiconductor substrate opposite to the first side, removing the sacrificial material in the trenches; and

filling the trenches with a conductive material.

28. The method of claim 27 , wherein

the first epitaxial layer comprises a first doping concentration,

the second epitaxial layer comprises a second doping concentration, and

the first doping concentration is higher than the second doping concentration.

29. The method of claim 27 , further comprising:

forming a device region in the second epitaxial layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 10, 2016
From: HELLMUND, OLIVER; MURI, INGO; BAUMGARTL, JOHANNES; MODER, IRIS; NEIDHART, THOMAS CHRISTIAN; SCHULZE, HANS-JOACHIM
To: INFINEON TECHNOLOGIES AG
Reel/Frame 039977/0910 →
Continuity (1)
Related Publication 20180040504A1 · Feb 8, 2018