Semiconductor structure with insertion layer and method for manufacturing the same
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, an interfacial layer formed over the substrate, and an insertion layer formed over the interfacial layer. The semiconductor structure further includes a gate dielectric layer formed over the insertion layer and a gate structure formed over the gate dielectric layer. The insertion layer and the gate dielectric layer may be metal oxides where the insertion layer has an oxygen coordination number greater than the gate dielectric layer.
1. A semiconductor structure, comprising:
an interfacial layer formed over a substrate;
an insertion layer formed over the interfacial layer, wherein the insertion layer includes a first composition of metal oxide;
a gate dielectric layer formed over the insertion layer, wherein the gate dielectric layer includes a second composition of metal oxide, wherein the first composition is M 1 O x and second composition is M 1 O y , and x is greater than y; and
a gate structure formed over the gate dielectric layer.
2. The semiconductor structure of claim 1 , wherein M 1 is selected from Hf, Al, Y, Ga, Sc, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu, O is oxygen, and y is a number greater than 0.
3. The semiconductor structure of claim 1 , wherein x is in a range from about 5 to about 10 and y is in a range of from about 1 to about 4.
4. The semiconductor structure of claim 1 , wherein a dielectric constant of the gate dielectric layer is greater than a dielectric constant of the insertion layer.
5. The semiconductor structure of claim 1 , wherein the gate structure includes a work function metal layer and a metal gate electrode layer.
6. A semiconductor structure, comprising:
a substrate having a fin structure extending from the substrate;
an interfacial layer formed over the fin structure;
an insertion layer formed over the interfacial layer;
a gate dielectric layer formed over the insertion layer and disposed over a top surface and at least one side surface of the fin structure; and
a gate structure formed over the gate dielectric layer,
wherein the insertion layer is made of a first metal oxide and the gate dielectric layer is made of a second metal oxide, wherein the first metal oxide has a higher coordination number than the second metal oxide.
7. The semiconductor structure of claim 6 , wherein the insertion layer is M 1 O x , where M 1 is a metal, O is oxygen, and x is in a range from about 5 to about 10.
8. The semiconductor structure of claim 7 , wherein the gate dielectric layer is made of M 2 O y , wherein M 2 is a metal, O is oxygen, and y is in a range from about 1 to about 4, wherein M 1 and M 2 may be a same metal or a different metal.
9. The semiconductor structure of claim 8 , wherein M 1 and M 2 are individually selected from Hf, Al, Y, Ga, Sc, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu.
10. The semiconductor structure of claim 8 , wherein M 1 and M 2 are the same metal.
11. The semiconductor structure of claim 6 , wherein a dielectric constant of the gate dielectric layer is greater than a dielectric constant of the insertion layer.
12. A method for manufacturing a semiconductor structure, comprising:
forming a dummy gate structure on a substrate;
removing the dummy gate structure to form a trench,
after removing the dummy gate structure, forming an interfacial layer over the substrate;
forming an insertion layer over the interfacial layer, wherein the insertion layer includes a first metal oxide composition;
forming a gate dielectric layer over the insertion layer, wherein the gate dielectric layer includes a second metal oxide composition, wherein the forming the insertion layer and the forming the gate dielectric layer includes forming the insertion layer and the gate dielectric layer within the trench; and
forming a gate structure over the gate dielectric layer,
wherein the insertion layer the first metal oxide composition has a greater oxygen content than the second metal oxide composition.
13. The method for manufacturing of claim 12 , wherein the insertion layer is made of M 1 m O n , M 1 is a metal, O is oxygen, m is a first value, and n is a second value and wherein a ratio of n to m is in a range from about 5 to about 10.
14. The method for manufacturing of claim 12 , wherein the forming the insertion layer includes performing a chemical vapor deposition process.
15. The method for manufacturing of claim 12 , wherein the forming the gate structure comprises:
depositing a work function metal layer directly over the gate dielectric layer; and
forming a gate electrode layer formed over the work function metal layer.
16. The method for manufacturing of claim 12 , wherein the forming the insertion layer includes performing a thermal process to grow the insertion layer on a top surface of the interfacial layer.
17. The method for manufacturing of claim 12 , wherein a dielectric constant of the insertion layer is greater than a dielectric constant of the interfacial layer.
18. The semiconductor structure of claim 1 , wherein M 1 is Hafnium (Hf).
19. The method for manufacturing of claim 12 , further comprising: forming a fin structure extending from the substrate, wherein the dummy gate is formed on the fin structure.
20. The semiconductor structure of claim 6 , wherein the first metal oxide is HfOx and the second metal oxide is HfOy, wherein x is greater than y.