Processing apparatus and processing system

1. A processing apparatus comprising:

a programmable logic circuit connected to an oscillator configured to output a first clock, the programmable logic circuit being configured to input the first clock; and

a memory storing circuit information of the programmable logic circuit, wherein

the programmable logic circuit comprises:

a phase synchronization circuit configured to generate and output a second clock with a frequency of a predetermined ratio with respect to a frequency of the first clock based on the first clock;

a detection unit provided on the phase synchronization circuit and configured to detect an asynchronous state of the first clock and the second clock to output a predetermined detection signal;

an arithmetic unit configured to execute a predetermined process based on the second clock;

a monitoring unit configured to detect a ratio between the frequencies of the first clock and the second clock, compare the detected ratio with the predetermined ratio, and output a predetermined abnormal signal when the detected ratio does not coincide with the predetermined ratio; and

an initialization unit configured to generate a reset signal when the monitoring unit outputs the abnormal signal, also generate the reset signal when the detection unit outputs the detection signal, and output the reset signal to the phase synchronization circuit and the arithmetic unit in either case.

2. A processing system comprising:

the processing apparatus according to claim 1 ; and

the oscillator configured to output the first clock to the programmable logic circuit.

3. A processing apparatus comprising:

a programmable logic circuit connected to an oscillator configured to output a first clock, the programmable logic circuit being configured to input the first clock; and

a memory storing circuit information of the programmable logic circuit, wherein

the programmable logic circuit comprises:

a phase synchronization circuit configured to generate and output a second clock with a frequency of a predetermined ratio with respect to a frequency of the first clock based on the first clock;

a detection unit provided on the phase synchronization circuit and configured to detect an asynchronous state of the first clock and the second clock to output a predetermined detection signal;

an arithmetic unit configured to execute a predetermined process based on the second clock;

a monitoring unit configured to compare two adjacent clock signals in the second clock and output a predetermined abnormal signal when detecting a predetermined phase difference; and

an initialization unit configured to generate a reset signal when the monitoring unit outputs the abnormal signal, also generate the reset signal when the detection unit outputs the detection signal, and output the reset signal to the phase synchronization circuit and the arithmetic unit in either case.

4. A processing system comprising:

the processing apparatus according to claim 3 ; and

the oscillator configured to output the first clock to the programmable logic circuit.

5. A processing apparatus comprising:

a programmable logic circuit connected to an oscillator configured to output a first clock, the programmable logic circuit being configured to input the first clock; and

a memory storing circuit information of the programmable logic circuit, wherein

the programmable logic circuit comprises:

a first phase synchronization circuit configured to generate and output a second clock with a frequency of a first predetermined ratio with respect to a frequency of the first clock based on the first clock;

a second phase synchronization circuit configured to generate and output a third clock with a frequency of a second predetermined ratio with respect to the frequency of the first clock based on the first clock;

a first detection unit provided on the first phase synchronization circuit and configured to detect an asynchronous state of the first clock and the second clock to output a predetermined first detection signal;

a second detection unit provided on the second phase synchronization circuit and configured to detect an asynchronous state of the first clock and the third clock to output a predetermined second detection signal;

an arithmetic unit comprising a first arithmetic circuit configured to execute a predetermined process based on the second clock and a second arithmetic circuit configured to execute a predetermined process based on the third clock;

a monitoring unit configured to output a predetermined abnormal signal when at least one of the second clock and the third clock is in a predetermined abnormal state; and

an initialization unit configured to generate a reset signal when the monitoring unit outputs the abnormal signal, also generate the reset signal when the first detection unit outputs the first detection signal, further generate the reset signal when the second detection unit outputs the second detection signal, and output the reset signal to the phase synchronization circuit and the arithmetic unit in any case.

6. The processing apparatus according to claim 5 , wherein

the monitoring unit outputs the abnormal signal when the monitoring unit detects a ratio between the frequencies of the first clock and the second clock, and the detected ratio does not coincide with the first predetermined ratio, and/or when the monitoring unit detects a ratio between the frequencies of the first clock and the third clock, and the detected ratio does not coincide with the second predetermined ratio.

7. A processing system comprising:

the processing apparatus according to claim 5 ; and

the oscillator configured to output the first clock to the programmable logic circuit.