IP Library › Granted Patent US 9,967,192
Granted Patent B2
US 9,967,192 · App. 15/049,941 · Granted May 8, 2018

Offloading of management controller traffic

Inventors: Li-Min Lin (Taoyuan, TW); Chih-Chia Huang (Taoyuan, TW); Ying-Chin Huang (Taoyuan, TW)
Assignee: QUANTA COMPUTER INC.
H04L47/125H04L43/08H04L49/25H04L49/70H04L67/1004
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Quick Facts
Patent No.
US 9,967,192
App. No.
15/049,941
Granted
May 8, 2018
Kind
B2
Abstract

A system for offloading management controller traffic includes a data port, an out-of-band port, and a leaf switch. The leaf switch includes a switch application-specific integrated circuit (ASIC) and an unmanaged chip directly connected to the switch ASIC. The switch ASIC is configured to direct data traffic to the data port and offload baseboard management controller (BMC) traffic to the unmanaged chip. The unmanaged chip is configured to direct the BMC traffic to the out-of-band port.

Claims (41)

1. A system for offloading server management traffic, comprising:

a data port;

an out-of-band port; and

a leaf switch comprising:

a processor;

a switch integrated circuit; and

an unmanaged chip directly connected to the switch integrated circuit, wherein the unmanaged chip is a physical circuit, and wherein management connectivity of the unmanaged chip is independent of the processor,

the switch integrated circuit configured to direct data traffic to the data port and offload baseboard management controller (BMC) traffic to the unmanaged chip,

the unmanaged chip configured to direct the BMC traffic to the out-of-band port.

2. The system of claim 1 , wherein the unmanaged chip is further configured to direct switch management traffic to the out-of-band port.

3. The system of claim 1 , wherein the unmanaged chip is configured to direct the BMC traffic to the out-of-band port using a media access control (MAC) table and a virtual local area network (VLAN) configuration.

4. The system of claim 1 , further comprising a processor and a BMC, wherein the BMC is connected to the processor.

5. The system of claim 1 , further comprising a processor, wherein the unmanaged chip is connected to the processor.

6. The system of claim 1 , wherein the unmanaged chip is connected to the switch integrated circuit.

7. The system of claim 1 , wherein the leaf switch is located in a top-of-rack (TOR).

8. The system of claim 1 , wherein the unmanaged chip is further configured to direct inbound management traffic from the out-of-band port to the switch integrated circuit and the switch integrated circuit is further configured to direct the inbound management traffic to the management controller.

9. A method for offloading server management traffic, comprising:

directing, by a switch integrated circuit of a leaf switch, data traffic to a data port, the leaf switch further comprising a processor;

offloading, by the switch integrated circuit, baseboard management controller (BMC) traffic to an unmanaged chip of the leaf switch, wherein the unmanaged chip is directly connected to the switch integrated circuit, wherein management connectivity of the unmanaged chip is independent of the processor, and wherein the unmanaged chip is a physical circuit; and

directing, by the unmanaged chip, the BMC traffic to an out-of-band port.

10. The method of claim 9 , further comprising directing, by the unmanaged chip, switch management traffic to the out-of-band port.

11. The method of claim 9 , wherein the unmanaged chip uses a media access control (MAC) table and a virtual local area network (VLAN) configuration to direct the BMC traffic to the out-of-band port.

12. A system for offloading server management traffic, comprising:

a data port;

an out-of-band port;

a leaf switch comprising:

a processor;

a switch integrated circuit connected to the processor; and

an unmanaged chip connected to the processor and directly connected to the switch integrated circuit, wherein the unmanaged chip is a physical circuit, and wherein management connectivity of the unmanaged chip is independent of the processor,

the switch integrated circuit configured to direct data traffic to the data port and offload baseboard management controller (BMC) traffic to the unmanaged chip,

the unmanaged chip configured to direct the BMC traffic to the out-of-band port, and

a BMC connected to the processor and to the unmanaged chip.

13. The system of claim 12 , wherein the unmanaged chip is further configured to direct switch management traffic to the out-of-band port.

14. The system of claim 12 , wherein the unmanaged chip uses a media access control (MAC) table and a virtual local area network (VLAN) configuration to direct the BMC traffic to the out-of-band port.

15. The system of claim 12 , further comprising a processor and a BMC, wherein the BMC is connected to the processor using a universal asynchronous receiver/transmitter (UART) interface.

16. The system of claim 12 , further comprising a processor, wherein the unmanaged chip is connected to the processor using a serial gigabit media independent interface (SGMII) interface or a serializer/deserializer (SerDes) interface.

17. The system of claim 12 , wherein the unmanaged chip is connected to the switch integrated circuit using an Ethernet interface.

18. The system of claim 12 , wherein the leaf switch is located in a top-of-rack (TOR).

19. The system of claim 12 , wherein the unmanaged chip is further configured to direct inbound management traffic from the out-of-band port to the switch integrated circuit and the switch integrated circuit is further configured to direct the inbound management traffic to the management controller.

20. The system of claim 12 , wherein the unmanaged chip is directly connected to the out-of-band port, and wherein the unmanaged chip is connected to a management server, via the out-of-band port, using an out-of-band connection.

21. The system of claim 12 , wherein the unmanaged chip is configured to use a MAC table and a virtual local area network (VLAN) configuration to direct traffic from the BMC to the out-of-band port.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2016
From: LIN, LI-MIN; HUANG, CHIH-CHIA; HUANG, YING-CHIN
To: QUANTA COMPUTER INC.
Reel/Frame 037789/0580 →
Continuity (1)
Related Publication 20170244640A1 · Aug 24, 2017