Memory devices, systems and methods employing command/address calibration
During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system.
1. A memory system comprising:
a memory controller; and
a memory device connected to the memory controller via a clock signal line, a command/address bus and a bi-directional data bus,
wherein the memory controller includes:
a clock generator configured to generate a clock signal, and to provide the clock signal to the memory device via the clock signal line;
a command/address generator configured to generate an initial command/address signal;
a command/address transmitter configured to receive the initial command/address signal, to generate a command/address signal based on the initial command/address signal, and to provide the command/address signal to the memory device via the command/address bus;
a register configured to store information of the command/address signal;
a comparator configured to receive the information of the command/address signal, and to compare the information of the command/address signal with information of a command/address calibration signal;
a phase/timing controller configured to generate a control signal, and to provide the control signal to the command/address transmitter; and
an input/output circuit configured to receive the information of the command/address calibration signal from the memory device via the bi-directional data bus.
2. The memory system of claim 1 , wherein the memory device includes:
a clock buffer configured to receive the clock signal;
a command/address receiver configured to receive the command/address signal; and
a data input/output circuit configured to output the information of the command/address calibration signal to the memory controller through the bi-directional data bus.
3. The memory system of claim 2 ,
wherein the command/address transmitter provides first data and second data to the memory device via the command/address bus, and
wherein the command/address receiver receives the first data at a rising edge of a first cycle of the clock signal through the command/address bus, and the second data at a falling edge of the first cycle of the clock signal through the command/address bus.
4. The memory system of claim 3 , wherein the command/address receiver generates first calibration information based on the first data, and to generate second calibration information based on the second data.
5. The memory system of claim 2 , wherein the command/address receiver receives a chip selection signal and a clock enable signal provided by the memory controller via one or more different signal lines from the command/address bus.
6. The memory system of claim 1 , wherein the command/address transmitter adjusts a phase or timing of the initial command/address signal in response to the control signal, in order to generate the command/address signal.
7. The memory system of claim 1 , wherein the comparator generates a pass or fail signal by comparing the information of the command/address signal with the information of the command/address calibration signal.
8. The memory system of claim 1 , wherein the memory controller includes a command/address generation reference circuit configured to generate a command/address reference signal that is transmitted to the memory device.
9. A memory system comprising:
a memory device; and
a memory controller connected to the memory device via a clock signal line, a command/address bus and a data bus, the memory controller including:
a clock generator configured to generate a clock signal, and to provide the clock signal to the memory device via the clock signal line;
a command/address transmitter configured to generate a command/address signal, and to provide the command/address signal, first data and second data to the memory device via the command/address bus; and
an input/output circuit configured to receive first calibration information and second calibration information from the memory device via the data bus,
wherein the memory device includes:
a clock buffer configured to receive the clock signal;
a command/address receiver configured to receive the command/address signal, to receive the first data at a rising edge of a first cycle of the clock signal through the command/address bus, to receive the second data at a falling edge of the first cycle of the clock signal through the command/address bus, to generate the first calibration information based on the first data, and to generate the second calibration information based on the second data; and
a data input/output circuit configured to receive the first calibration information and the second calibration information, and to output the first calibration information and the second calibration information to the memory controller through the data bus.
10. The memory system of claim 9 , wherein the memory controller further includes:
a command/address generator configured to generate an initial command/address signal;
a register configured to store information of the command/address signal;
a comparator configured to compare the information of the command/address signal with information of a command/address calibration signal; and
a phase/timing controller configured to generate a control signal, and to provide the control signal to the command/address transmitter.
11. The memory system of claim 10 , wherein the comparator generates a pass or fail signal by comparing the information of the command/address signal with the information of the command/address calibration signal.
12. The memory system of claim 11 , wherein the phase/timing controller generates the control signal based on the pass or fail signal.
13. The memory system of claim 9 , wherein, in a normal operation mode, the input/output circuit receives read data transmitted from the memory device through the data bus or transmits write data to the memory device through the data bus.
14. The memory system of claim 9 , wherein, in a calibration mode, the input/output circuit receives the first calibration information and the second calibration information from the memory device.
15. The memory system of claim 9 , wherein the data bus is bi-directional.
16. A memory device comprising:
a clock buffer configured to receive a clock signal through a clock signal line, and to generate an internal clock signal;
a command/address receiver configured to receive a calibration command through a command/address bus, to receive first data at a rising edge of a first cycle of the clock signal through the command/address bus, to receive second data at a falling edge of the first cycle of the clock signal through the command/address bus, to generate first calibration information based on the first data in response to the internal clock signal, and to generate second calibration information based on the second data in response to the internal clock signal; and
a data input/output circuit configured to receive the first calibration information and the second calibration information, and to output the first calibration information and the second calibration information through a data bus.
17. The memory device of claim 16 , wherein, in a normal operation mode, the data input/output circuit transmits read data through the data bus and/or receives write data through the data bus.
18. The memory device of claim 16 , wherein, in a calibration mode, the data input/output circuit transmits the first calibration information and the second calibration information through the data bus.
19. The memory device of claim 16 , wherein the command/address receiver receives a chip selection signal and a clock enable signal.
20. The memory device of claim 16 , wherein the data bus is bi-directional.