Sensing circuit for resistive memory

1. A circuit, comprising:

a ramp generator to apply a voltage ramp to a resistive memory cell; and

a sensing circuit to enable the ramp generator and to monitor a current output received from the resistive memory cell in response to the voltage ramp,

wherein the sensing circuit compares the current output to a predetermined current threshold to determine a state of the resistive memory cell, and

wherein the sensing circuit comprises a current threshold circuit that compares a sample of the current output to a predetermined high threshold current and compares the sample of the current output to a predetermined low threshold current, the sensing circuit determining the state of the resistive memory cell based on the comparisons.

2. The circuit of claim 1 , wherein the sensing circuit further comprises a sample and hold circuit to provide sneak current subtraction from the resistive memory cell as the voltage ramp is applied to the resistive memory cell.

3. The circuit of claim 1 , further comprising a delay line to delay a given logic event in response to the comparison between the sample of the current output and the predetermined low threshold current.

4. The circuit of claim 3 , wherein the sensing circuit further comprises a logic circuit to receive the given logic event that propagates though the delay line and to receive a comparison output based on the comparison between the sample of the current output and the predetermined high threshold current.

5. The circuit of claim 4 , wherein the logic circuit is to determine the state of the resistive memory cell as a low resistance state if the sample of the current output reaches the predetermined high threshold current before the given logic event propagates through the delay line, and

wherein the logic circuit is to determine the state of the resistive memory cell as a high resistance state if the given logic event propagates though the delay line before the current output reaches the predetermined high threshold current.

6. The circuit of claim 5 , wherein the logic circuit is to disable the ramp generator in response to the state of the resistive memory cell being determined.

7. The circuit of claim 6 , wherein the logic circuit includes a latch to capture a logic state of the resistive memory cell based on the determined resistance state of the resistive memory cell.

8. The circuit of claim 1 , wherein the resistive memory cell is configured as one of plurality of resistive memory cells in horizontal cross-point array.

9. A circuit, comprising:

a resistive memory cell;

a ramp generator to apply a voltage ramp to the resistive memory cell;

a current threshold circuit that receives a current output from the resistive memory cell in response to the voltage ramp, wherein the current threshold circuit compares the current output from the resistive memory cell to a high threshold current and a low threshold current;

a delay line to delay a logic event signal corresponding to the current output reaching the low threshold current; and

a logic circuit that receives the logic event signal via the delay line in response to the current output reaching the low threshold current, the logic circuit to determine a state of the resistive memory cell as one resistance state if the current output reaches the low threshold current before the logic event propagates through the delay line, and the logic circuit to determine the state of the resistive memory cell as another resistance state if the logic event propagates though the delay line before the current output reaches a high threshold current.

10. The circuit of claim 9 , wherein the logic circuit disables the ramp generator in response to the state of the resistive memory cell being determined.

11. The circuit of claim 10 , wherein the logic circuit further comprises a latch to capture a logic state of the resistive memory cell based on the determined resistance state of the resistive memory cell.

12. The circuit of claim 9 , wherein the voltage ramp increases linearly from a starting voltage to a read voltage.

13. A method, comprising:

applying, via a controller, a voltage ramp to a resistive memory cell;

monitoring, via the controller, a current output received from the resistive memory cell in response to the voltage ramp;

comparing, via the controller, the current output to a predetermined low current threshold and a predetermined high current threshold to determine a state of the resistive memory cell;

delaying through a delay line a logic event responsive to the comparing the current output to the predetermined low current threshold;

determining a low resistance state if the current output reaches the predetermined high current threshold before the logic event propagates through the delay line; and

determining a high resistance state if the logic event propagates though the delay line before the current output reaches the predetermined high current threshold.