Semiconductor device
An IGBT includes an n-type drift layer, a p-type base layer and an n-type emitter layer formed on an upper surface of the n-type drift layer, and a p-type collector layer on a lower surface of the n-type drift layer. A FWD includes the n-type drift layer, a p-type anode layer formed on the upper surface of the n-type drift layer and an n-type cathode layer formed on the lower surface of the n-type drift layer. A p-type well is formed on the upper surface of the n-type drift layer in a wiring region and a termination region. A wiring is formed on the p-type well in the wiring region. The p-type well has a higher impurity concentration and is deeper than the p-type anode layer. The p-type well is not formed directly above the n-type cathode layer and is separate from a region directly above the n-type cathode layer.
1. A semiconductor device comprising:
an IGBT (Insulated Gate Bipolar Transistor) including an n-type drift layer, a p-type base layer and an n-type emitter layer formed on an upper surface of the n-type drift layer, and a p-type collector layer formed on a lower surface of the n-type drift layer;
a FWD (Free Wheeling Diode) including the n-type drift layer, a p-type anode layer formed on the upper surface of the n-type drift layer and an n-type cathode layer formed on the lower surface of the n-type drift layer;
a p-type well formed on the upper surface of the n-type drift layer in a wiring region and a termination region; and
a wiring formed on the p-type well in the wiring region,
wherein the p-type well has a higher impurity concentration and is deeper than the p-type anode layer,
the p-type well is not formed directly above the n-type cathode layer and is separate from a region directly above the n-type cathode layer, and
the p-type well is separate from the region directly above the n-type cathode layer by at least a thickness of the n-type drift layer, and
the wiring formed on the p-type well in the wiring region is connected to a small signal electrode, a magnitude of a small signal in the small signal electrode being less than a magnitude of a signal through the emitter and collector layers when the IGBT is in an on state.
2. The semiconductor device according to claim 1 , wherein the n-type emitter layer is not formed in a region of the FWD, and
the p-type base layer and the p-type anode layer have the same depth and concentration.
3. The semiconductor device according to claim 1 , wherein the IGBT is formed in a region between the wiring region and the termination region, and the FWD.
4. The semiconductor device according to claim 1 , wherein the IGBT and the FWD are repeatedly formed at a certain interval in a plan view.
5. The semiconductor device according to claim 1 , wherein the IGBT includes a gate electrode and the wiring is connected to the gate electrode.
6. A semiconductor device comprising:
an IGBT including an n-type drift layer, a p-type base layer and an n-type emitter layer formed on an upper surface of the n-type drift layer, and a p-type collector layer formed on a lower surface of the n-type drift layer;
a FWD including the n-type drift layer, a p-type anode layer formed on the upper surface of the n-type drift layer and an n-type cathode layer formed on the lower surface of the n-type drift layer;
a p-type well formed on the upper surface of the n-type drift layer in a wiring region and a termination region; and
a wiring formed on the p-type well in the wiring region,
wherein the p-type well is deeper and has a lower impurity concentration than the p-type anode layer, and
the wiring formed on the p-type well in the wiring region is connected to a small signal electrode, a magnitude of a small signal in the small signal electrode being less than a magnitude of a signal through the emitter and collector layers when the IGBT is in an on state.
7. The semiconductor device according to claim 6 , wherein the IGBT includes a gate electrode and the wiring is connected to the gate electrode.
8. A semiconductor device comprising:
an IGBT including an n-type drift layer, a p-type base layer and an n-type emitter layer formed on an upper surface of the n-type drift layer, and a p-type collector layer formed on a lower surface of the n-type drift layer;
a FWD including the n-type drift layer, a p-type anode layer formed on the upper surface of the n-type drift layer and an n-type cathode layer formed on the lower surface of the n-type drift layer;
a p-type well formed on the upper surface of the n-type drift layer in a wiring region and a termination region; and
a wiring formed on the p-type well in the wiring region,
wherein the p-type well has the same impurity concentration and the same depth as those of the p-type anode layer, and
the p-type anode layer is directly connected to the p-type well.
9. The semiconductor device according to claim 8 , wherein the p-type well and the p-type anode layer are formed by simultaneously injecting and diffusing P-type impurity.