IP Library › Granted Patent US 9,972,624

Granted Patent B2

US 9,972,624 · App. 13/975,185 · Granted May 15, 2018

Layout construction for addressing electromigration

Inventors: Seid Hadi Rasouli (San Diego, CA); Michael Joseph Brunolli (Escondido, CA); Christine Sung-An Hau-Riege (Fremont, CA); Mickael Malabry (San Diego, CA); Sucheta Kumar Harish (San Diego, CA); Prathiba Balasubramanian (Bangalore, IN); Kamesh Medisetti (Bangalore, IN); Nikolay Bomshtein (San Diego, CA); Animesh Datta (San Diego, CA); Ohsang Kwon (San Diego, CA)

Assignee: QUALCOMM Incorporated

H01L27/0921 H01L21/823871 H01L23/4824 H01L27/0207 H01L27/092 H03K17/168 H03K17/6872 H01L23/522 H01L2924/0002

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Quick Facts

Patent No.: US 9,972,624
App. No.: 13/975,185
Granted: May 15, 2018
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect on an interconnect level extending in a length direction to connect the PMOS drains together. A second interconnect on the interconnect level extends in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level couple the first interconnect and the second interconnect together. A third interconnect on the interconnect level extends perpendicular to the length direction and is offset from the set of interconnects to connect the first interconnect and the second interconnect together.

Claims (34)

1. A complementary metal oxide semiconductor (CMOS) device including a plurality of p-type metal oxide semiconductor (PMOS) transistors each having a PMOS drain and a plurality of n-type metal oxide semiconductor (NMOS) transistors each having an NMOS drain, comprising:

a first interconnect on an interconnect level extending in a length direction to connect the PMOS drains together;

a second interconnect on the interconnect level extending in the length direction to connect the NMOS drains together;

a set of interconnects on at least one additional interconnect level physically coupling the first interconnect and the second interconnect together; and

a third interconnect on the interconnect level extending perpendicular to the length direction and offset from the set of interconnects to connect the first interconnect and the second interconnect together.

2. The device of claim 1 , further comprising a fourth interconnect on the interconnect level extending perpendicular to the length direction and offset from the set of interconnects to connect the first interconnect and the second interconnect together, the third interconnect and the fourth interconnect being on opposite sides of the set of interconnects.

3. The device of claim 2 , wherein the at least one additional interconnect level comprises a second interconnect level and a third interconnect level, and the set of interconnects comprises:

a fifth interconnect on the second interconnect level coupled to the first interconnect;

a sixth interconnect on the second interconnect level coupled to the second interconnect; and

a seventh interconnect on the third interconnect level coupling the fifth interconnect and the sixth interconnect together.

4. The device of claim 3 , wherein the seventh interconnect is an output of the device.

5. The device of claim 3 , wherein the third interconnect and the fourth interconnect are parallel to the seventh interconnect and are offset by at least a distance d from the seventh interconnect.

6. The device of claim 5 , wherein the distance d is approximately equal to a distance such that a first current flowing in the first interconnect between the third interconnect and the seventh interconnect upon turning the PMOS transistors on and the NMOS transistors off is approximately equal to a second current flowing in the first interconnect between the seventh interconnect and the third interconnect upon turning the PMOS transistors off and the NMOS transistors on.

7. The device of claim 5 , wherein the distance d is approximately equal to a distance such that a first current flowing in the first interconnect between the fourth interconnect and the seventh interconnect upon turning the PMOS transistors on and the NMOS transistors off is approximately equal to a second current flowing in the first interconnect between the seventh interconnect and the fourth interconnect upon turning the PMOS transistors off and the NMOS transistors on.

8. The device of claim 5 , wherein the distance d is approximately equal to a distance such that a first current flowing in the second interconnect between the third interconnect and the seventh interconnect upon turning the PMOS transistors on and the NMOS transistors off is approximately equal to a second current flowing in the second interconnect between the seventh interconnect and the third interconnect upon turning the PMOS transistors off and the NMOS transistors on.

9. The device of claim 5 , wherein the distance d is approximately equal to a distance such that a first current flowing in the second interconnect between the fourth interconnect and the seventh interconnect upon turning the PMOS transistors on and the NMOS transistors off is approximately equal to a second current flowing in the second interconnect between the seventh interconnect and the fourth interconnect upon turning the PMOS transistors off and the NMOS transistors on.

10. The device of claim 1 , wherein the CMOS device is an inverter, the PMOS transistors each have a PMOS gate and a PMOS source, the NMOS transistors each have an NMOS gate and an NMOS source, the NMOS sources of the NMOS transistors being coupled together, the PMOS sources of the PMOS transistors being coupled together, the PMOS gates of the PMOS transistors and the NMOS gates of the NMOS transistors being coupled together.

11. A complementary metal oxide semiconductor (CMOS) device including a plurality of p-type metal oxide semiconductor (PMOS) transistors each having a PMOS drain and a plurality of n-type metal oxide semiconductor (NMOS) transistors each having an NMOS drain, comprising:

means for interconnecting the PMOS drains with a first interconnect on an interconnect level extending in a length direction;

means for interconnecting the NMOS drains with a second interconnect on the interconnect level extending in the length direction;

means for physically interconnecting the first interconnect and the second interconnect with a set of interconnects on at least one additional interconnect level; and

means for interconnecting the first interconnect and the second interconnect with a third interconnect on the interconnect level extending perpendicular to the length direction and offset from the set of interconnects.

12. The device of claim 11 , further comprising means for interconnecting the first interconnect and the second interconnect with a fourth interconnect on the interconnect level extending perpendicular to the length direction and offset from the set of interconnects, the third interconnect and the fourth interconnect being on opposite sides of the set of interconnects.

13. The device of claim 12 , wherein the at least one additional interconnect level comprises a second interconnect level and a third interconnect level, and the set of interconnects comprises:

a fifth interconnect on the second interconnect level coupled to the first interconnect;

a sixth interconnect on the second interconnect level coupled to the second interconnect; and

a seventh interconnect on the third interconnect level coupling the fifth interconnect and the sixth interconnect together.

14. The device of claim 13 , wherein the seventh interconnect is an output of the device.

15. The device of claim 13 , wherein the third interconnect and the fourth interconnect are parallel to the seventh interconnect and are offset by at least a distance d from the seventh interconnect.

16. The device of claim 15 , wherein the distance d is approximately equal to a distance such that a first current flowing in the first interconnect between the third interconnect and the seventh interconnect upon turning the PMOS transistors on and the NMOS transistors off is approximately equal to a second current flowing in the first interconnect between the seventh interconnect and the third interconnect upon turning the PMOS transistors off and the NMOS transistors on.

17. The device of claim 15 , wherein the distance d is approximately equal to a distance such that a first current flowing in the first interconnect between the fourth interconnect and the seventh interconnect upon turning the PMOS transistors on and the NMOS transistors off is approximately equal to a second current flowing in the first interconnect between the seventh interconnect and the fourth interconnect upon turning the PMOS transistors off and the NMOS transistors on.

18. The device of claim 15 , wherein the distance d is approximately equal to a distance such that a first current flowing in the second interconnect between the third interconnect and the seventh interconnect upon turning the PMOS transistors on and the NMOS transistors off is approximately equal to a second current flowing in the second interconnect between the seventh interconnect and the third interconnect upon turning the PMOS transistors off and the NMOS transistors on.

19. The device of claim 15 , wherein the distance d is approximately equal to a distance such that a first current flowing in the second interconnect between the fourth interconnect and the seventh interconnect upon turning the PMOS transistors on and the NMOS transistors off is approximately equal to a second current flowing in the second interconnect between the seventh interconnect and the fourth interconnect upon turning the PMOS transistors off and the NMOS transistors on.

20. The device of claim 11 , wherein the CMOS device is an inverter, the PMOS transistors each have a PMOS gate and a PMOS source, the NMOS transistors each have an NMOS gate and an NMOS source, the NMOS sources of the NMOS transistors being coupled together, the PMOS sources of the PMOS transistors being coupled together, the PMOS gates of the PMOS transistors and the NMOS gates of the NMOS transistors being coupled together.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 12, 2014

From: RASOULI, SEID HADI; BRUNOLLI, MICHAEL JOSEPH; HAU-RIEGE, CHRISTINE SUNG-AN; MALABRY, MICKAEL; HARISH, SUCHETA KUMAR; BALASUBRAMANIAN, PRATHIBA; MEDISETTI, KAMESH; BOMSHTEIN, NIKOLAY; DATTA, ANIMESH; KWON, OHSANG

To: QUALCOMM INCORPORATED

Reel/Frame 032209/0550 →

Continuity (1)

Related Publication 20150054568A1 · Feb 26, 2015