Solid-state imaging apparatus and method for manufacturing the solid-state imaging apparatus having sealing portion disposed in bonded members

1. A solid-state imaging apparatus comprising

a first semiconductor substrate which is provided with a photoelectric conversion unit and a first transistor;

a second semiconductor substrate which is provided with a second transistor;

a plurality of wiring layers, a first wiring layer of the plurality of wiring layers including a first conductive pattern connected to the first transistor, and a second wiring layer of the plurality of wiring layers including a second conductive pattern connected to the second transistor; and

an insulating member,

wherein the first semiconductor substrate and the second semiconductor substrate are laminated in such a way that the insulating member and the plurality of wiring layers are disposed between the first semiconductor substrate and the second semiconductor substrate,

wherein the first wiring layer includes a third conductive pattern, the second wiring layer includes a fourth conductive pattern,

a sealing portion is constituted by the third conductive pattern and the fourth conductive pattern, and

a wiring layer of the plurality of wiring layers includes a fifth conductive pattern, and

wherein the fifth conductive pattern is surrounded by the sealing portion in a plane view.

2. The solid-state imaging apparatus according to claim 1 ,

wherein a third wiring layer of the plurality of wiring layers and a fourth wiring layer of the plurality of wiring layers are arranged between the first wiring layer and the second wiring layer,

wherein the third wiring layer includes a sixth conductive pattern connected to the first conductive pattern and includes a seventh conductive pattern, and the fourth wiring layer includes an eighth conductive pattern connected to the second conductive pattern and includes a ninth conductive pattern,

wherein the sixth conductive pattern is in contact with the eighth conductive pattern, and the seventh conductive pattern is in contact with the ninth conductive pattern, and

wherein the sealing portion is further constituted by the seventh conductive pattern and the ninth conductive pattern.

3. The solid-state imaging apparatus according to claim 1 , wherein the plurality of wiring layers is laminated via interlayer insulating layers, and the plurality of wiring layers are electrically connected to each other via a plug penetrating each interlayer insulating layer, and

the sealing portion is further constituted by the plug.

4. The solid-state imaging apparatus according to claim 1 , wherein

a first wiring structure provided on the first semiconductor substrate, and includes the first wiring layer,

a second wiring structure is provided on the second semiconductor substrate, and includes the second wiring layer, and wherein

the sealing portion comprising a first sealing portion and a second sealing portion, and

the first sealing portion is constituted by a part of the first wiring structure, and the second sealing portion is constituted by a part of the second wiring structure.

5. The solid-state imaging apparatus according to claim 4 , wherein an area of the first semiconductor substrate where the plurality of photoelectric conversion units is disposed is positioned inside an area where the first sealing portion is projected on the first semiconductor substrate.

6. The solid-state imaging apparatus according to claim 5 , wherein an area of the second semiconductor substrate where the transistor is disposed is positioned inside an area where the second sealing portion is projected on the second semiconductor substrate.

7. The solid-state imaging apparatus according to claim 4 , further comprising:

a plurality of pads capable of inputting a signal from an external circuit or outputting a signal to an external circuit,

wherein the plurality of pads are constituted by a part of the first wiring structure, and

an area where the plurality of pads are projected on the second semiconductor substrate is surrounded by an area where the first sealing portion are projected on the second semiconductor substrate.

8. The solid-state imaging apparatus according to claim 1 , wherein the first conductive pattern is surrounded by the third conductive pattern in the plane view.

9. The solid-state imaging apparatus according to claim 8 , wherein the second conductive pattern is surrounded by the fourth conductive pattern in the plane view.

10. The solid-state imaging apparatus according to claim 2 , wherein the sixth conductive pattern is surrounded by the seventh conductive pattern in the plane view.

11. The solid-state imaging apparatus according to claim 10 , wherein the eighth conductive pattern is surrounded by the ninth conductive pattern in the plane view.

12. The solid-state imaging apparatus according to claim 4 , wherein the first sealing portion is in contact with the second sealing portion.

13. The solid-state imaging apparatus according to claim 2 , wherein the wiring layer which including the fifth conductive pattern is arranged between the third wiring layer and the first semiconductor substrate.

14. The solid-state imaging apparatus according to claim 2 , wherein the wiring layer including the fifth conductive pattern is arranged between the fourth wiring layer and the second semiconductor substrate.

15. A solid-state imaging apparatus comprising:

a first semiconductor substrate which is provided with a photoelectric conversion unit and a first transistor;

a second semiconductor substrate which is provided with a second transistor;

a plurality of wiring layers, a first wiring layer of the plurality of wiring layers including a first conductive pattern connected to the first transistor, and a second wiring layer of the plurality of wiring layers including a second conductive pattern connected to the second transistor; and

an insulating member,

wherein the first semiconductor substrate and the second semiconductor substrate are laminated in such a way that the insulating member and the plurality of wiring layers are disposed between the first semiconductor substrate and the second semiconductor substrate,

wherein the first wiring layer includes a third conductive pattern, and the second wiring layer includes a fourth conductive pattern,

wherein a sealing portion is constituted by the third conductive pattern and the fourth conductive pattern, and

wherein the first semiconductor substrate and the insulating member are provided with an opening,

wherein the opening of the the insulating member is surrounded by the sealing portion in a plane view.

16. The solid-state imaging apparatus according to claim 15 ,

wherein the first conductive pattern is in contact with the second conductive pattern, and the third conductive pattern is in contact with the fourth conductive pattern.

17. The solid-state imaging apparatus according to claim 15 , wherein the opening of the the insulating member is surrounded by the third conductive pattern in the plane view.

18. The solid-state imaging apparatus according to claim 15 , wherein a wiring layer of the plurality of wiring layers includes a fifth conductive pattern, and the fifth conductive pattern is arranged between the opening of the the insulating member and the second semiconductor substrate.

19. The solid-state imaging apparatus according to claim 18 , wherein the third conductive pattern and the fourth conductive pattern are arranged between the fifth conductive pattern and the first semiconductor substrate.

20. The solid-state imaging apparatus according to claim 19 , wherein the insulating member is constituted by a silicon oxide film and a layer containing SiN or SiON.