Semiconductor device and method of manufacturing same
To provide a semiconductor device including a power semiconductor element having improved reliability. The semiconductor device has a cell region and a peripheral region formed outside the cell region. The n type impurity concentration of n type column regions in the cell region is made higher than that of n type column regions comprised of an epitaxial layer in the peripheral region. Further, a charge balance is kept in each of the cell region and the peripheral region and each total electric charge is set so that a total electric charge of first p type column regions and a total electric charge of n type column regions in the cell region become larger than a total electric charge of third p type column regions and n type column regions comprised of an epitaxial layer in the peripheral region, respectively.
1. A semiconductor device equipped with a semiconductor chip having a cell region and a peripheral region formed outside the cell region, and a transition region between the cell region and the peripheral region, the semiconductor chip comprising:
(a) a semiconductor substrate,
(b) an epitaxial layer of a first conductivity type formed over the main surface of the semiconductor substrate,
(c) first column regions of the first conductivity type formed in the epitaxial layer in the cell region while being separated from each other,
(d) a plurality of second column regions of a second conductivity type, which is a conductivity type different from the first conductivity type, formed in the epitaxial layer in the cell region while being sandwiched between the first column regions adjacent to each other,
(e) third column regions of the first conductivity type formed in the epitaxial layer in the peripheral region while being separated from each other,
(f) a plurality of fourth column regions of the second conductivity type formed in the epitaxial layer in the peripheral region while being sandwiched between the third column regions adjacent to each other, and
(g) an element portion formed over an upper surface of the epitaxial layer,
(h) fifth column regions of the first conductivity type formed in the epitaxial layer in the transition region while being separated from each other, and (i) a plurality of sixth column regions of the second conductivity type formed in the epitaxial layer in the transition region while being sandwiched between the fifth column regions adjacent to each other,
wherein a concentration of an impurity of a first conductivity type of the first column regions in the cell region is higher than a concentration of an impurity of the first conductivity type of the third column regions in the peripheral region,
wherein, in the cell region, a total electric charge of the second column regions is larger than a total electric charge of the first column regions,
wherein, in the peripheral region, a total electric charge of the fourth column regions is larger than a total electric charge of the third column regions,
wherein, in the cell region, a concentration of an impurity of the second conductivity type in the second column regions gradually decreases in a direction extending from the upper surface to a lower surface of the epitaxial layer,
wherein the concentration of the impurity of the second conductivity type in the second column regions is highest at the upper surface which is opposite the lower surface,
wherein the concentration of the impurity of the first conductivity type in the first column regions is uniform from the upper surface to the lower surface,
wherein a field intensity has a maximum value at a position deeper than an intermediate point in the direction from the upper surface to the lower surface of the epitaxial layer
wherein a concentration of an impurity of the first conductivity type of the fifth column regions in the transition region is lower than the first conductivity type impurity concentration of the first column regions in the cell region, and
wherein a concentration of an impurity of the second conductivity type of the sixth column regions in the transition region is higher than the second conductivity type impurity concentration of the fourth column regions in the peripheral region.
2. The semiconductor device according to claim 1 ,
wherein the total electric charge of the first column regions in the cell region is larger than the total electric charge of the third column regions in the peripheral region and the total electric charge of the second column regions in the cell region is larger than the total electric charge of the fourth column regions of the peripheral region.
3. The semiconductor device according to claim 1 ,
wherein the second column regions in the cell region each comprise a trench extending from the upper surface to the lower surface of the epitaxial layer and a semiconductor film of the second conductivity type which has filled the trench, and
wherein the trench has a width gradually narrowing in a direction extending from the upper surface to the lower surface of the epitaxial layer.
4. The semiconductor device according to claim 1 ,
wherein in the transition region, a difference between a total electric charge of the fifth column regions and a total electric charge of the sixth column regions falls within a range of ±10% of the total electric charge of the sixth column regions or the total electric charge of the sixth column regions is larger than the total electric charge of the fifth column regions.
5. The semiconductor device according to claim 4 ,
wherein the total electric charge of the fifth column regions in the transition region is smaller than a total electric charge of the first column regions in the cell region and larger than a total electric charge of the third column regions in the peripheral region, and the total electric charge of the sixth column regions in the transition region is smaller than a total electric charge of the second column regions in the cell region and larger than a total electric charge of the fourth column regions in the peripheral region.
6. The semiconductor device according to claim 1 ,
wherein an avalanche breakdown voltage in the cell region is lower than an avalanche breakdown voltage in the peripheral region.
7. A semiconductor device equipped with a semiconductor chip having a cell region and a peripheral region formed outside the cell region, the semiconductor chip comprising:
(a) a semiconductor substrate,
(b) an epitaxial layer of a first conductivity type formed over the main surface of the semiconductor substrate,
(c) first column regions of the first conductivity type formed in the epitaxial layer in the cell region while being separated from each other,
(d) a plurality of second column regions of a second conductivity type, which is a conductivity type different from the first conductivity type, formed in the epitaxial layer in the cell region while being sandwiched between the first column regions adjacent to each other,
(e) third column regions of the first conductivity type formed in the epitaxial layer in the peripheral region while being separated from each other,
(f) a plurality of fourth column regions of the second conductivity type formed in the epitaxial layer in the peripheral region while being sandwiched between the third column regions adjacent to each other, and
(g) an element portion formed over an upper surface of the epitaxial layer,
wherein a concentration of an impurity of a first conductivity type of the first column regions in the cell region is higher than a concentration of an impurity of the first conductivity type of the third column regions in the peripheral region,
wherein, in the cell region, a total electric charge of the second column regions is larger than a total electric charge of the first column regions,
wherein, in the peripheral region, a total electric charge of the fourth column regions is larger than a total electric charge of the third column regions,
wherein, in the cell region, a concentration of an impurity of the first conductivity type in the first column regions gradually increases in a direction extending from the upper surface to a lower surface of the epitaxial layer, and
wherein the concentration of the impurity of the first conductivity type in the first column regions is highest at the lower surface which is opposite the upper surface, and
wherein a concentration of impurity of the second conductivity type in the second column region is highest at the upper surface which is opposite the lower surface.
8. The semiconductor device according to claim 7 ,
wherein the total electric charge of the first column regions in the cell region is larger than the total electric charge of the third column regions in the peripheral region and the total electric charge of the second column regions in the cell region is larger than the total electric charge of the fourth column regions of the peripheral region.
9. The semiconductor device according to claim 7 ,
wherein the second column regions in the cell region each comprise a trench extending from the upper surface to the lower surface of the epitaxial layer and a semiconductor film of the second conductivity type which has filled the trench, and
wherein the trench has a width gradually narrowing in a direction extending from the upper surface to the lower surface of the epitaxial layer.
10. The semiconductor device according to claim 7 ,
wherein the semiconductor chip has a transition region between the cell region and the peripheral region, and
the semiconductor chip further comprises:
(h) fifth column regions of the first conductivity type formed in the epitaxial layer in the transition region while being separated from each other, and
(i) a plurality of sixth column regions of the second conductivity type formed in the epitaxial layer in the transition region while being sandwiched between the fifth column regions adjacent to each other,
wherein a concentration of an impurity of the first conductivity type of the fifth column regions in the transition region is lower than the first conductivity type impurity concentration of the first column regions in the cell region.
11. The semiconductor device according to claim 10 ,
wherein in the transition region, a difference between a total electric charge of the fifth column regions and a total electric charge of the sixth column regions falls within a range of ±10% of the total electric charge of the sixth column regions or the total electric charge of the sixth column regions is larger than the total electric charge of the fifth column regions.
12. The semiconductor device according to claim 11 ,
wherein the total electric charge of the fifth column regions in the transition region is smaller than a total electric charge of the first column regions in the cell region and larger than a total electric charge of the third column regions in the peripheral region, and the total electric charge of the sixth column regions in the transition region is smaller than a total electric charge of the second column regions in the cell region and larger than a total electric charge of the fourth column regions in the peripheral region.
13. The semiconductor device according to claim 7 ,
wherein an avalanche breakdown voltage in the cell region is lower than an avalanche breakdown voltage in the peripheral region.