Output stage circuit

1. An output stage circuit, comprising:

a power inverter, coupled to a signal terminal, and comprising at least two pairs of complementary metal-oxide-semiconductors (CMOS) cascaded together; and

a dynamic bias circuit, wherein the dynamic bias circuit connects between a system voltage terminal and the power inverter, the dynamic bias circuit comprises:

at least one Zener diode, configured to maintain a voltage difference between a gate terminal and a source terminal of at least one transistor of the power inverter within a first absolute value range;

configured to maintain a voltage difference between the gate terminal and a drain terminal of the at least one transistor within a second absolute value range; and

configured to maintain a voltage difference between the drain terminal and the source terminal of the at least one transistor within the second absolute value range.

2. The output stage circuit of claim 1 , wherein the at least one Zener diode bridges between the gate terminal and the source terminal of the at least one transistor, and an anode of the at least one Zener diode connects to the gate terminal, a cathode of the at least one Zener diode connects to the source terminal.

3. The output stage circuit of claim 1 , wherein the at least one Zener diode bridges between the gate terminal and the source terminal of the at least one transistor, and an anode of the at least one Zener diode connects to the source terminal, a cathode of the at least one Zener diode connects to the gate terminal.

4. The output stage circuit of claim 1 , wherein the dynamic bias circuit further comprises:

at least one resistance connected with the at least one Zener diode in parallel.

5. The output stage circuit of claim 1 , wherein the dynamic bias circuit further comprises:

at least one diode connected between the system voltage terminal and the gate terminal,

wherein an anode of the at least one diode connects to the gate terminal, a cathode of the at least one diode connects to the system voltage terminal.

6. The output stage circuit of claim 1 , wherein the dynamic bias circuit further comprises:

another diode connected between the system voltage terminal and the gate terminal,

wherein an anode of said another diode connects to the system voltage terminal, a cathode of said another diode connects to the gate terminal.

7. The output stage circuit of claim 1 , further comprises:

a protection circuit connected to the power inverter, configured to guide transient over voltage, the protection circuit comprises:

at least one transistor,

wherein a gate terminal of the at least one transistor couples to the signal terminal, a source terminal of the at least one transistor is grounded, a drain terminal of the at least one transistor of the protection circuit connects to the source terminal of the at least one transistor of the power inverter.

8. The output stage circuit of claim 1 , further comprises:

a protection circuit connected to the power inverter, configured to guide transient over voltage, the protection circuit comprises:

at least one transistor,

wherein a gate terminal of the at least one transistor couples to the signal terminal, a source terminal of the at least one transistor is grounded, a drain terminal of the at least one transistor of the protection circuit connects to the source terminal of the at least one transistor of the power inverter.

9. The output stage circuit of claim 1 , further comprises:

at least one level shifter,

wherein the at least one level shifter respectively connects to the signal terminal, the system voltage terminal, and a gate terminal of the power inverter.

10. The output stage circuit of claim 1 , wherein the system voltage comprises:

a first high voltage terminal, wherein the first high voltage terminal connects to a source terminal of the power inverter;

a second high voltage terminal, configured that an output voltage of the first high voltage terminal is higher than an output voltage of the second high voltage terminal, and the output voltages of the first and second high voltage terminals are positive values;

a first low voltage terminal, wherein the first low voltage terminal connects to a source terminal of the power inverter; and

a second low voltage terminal, configured that an output voltage of the first low voltage terminal is smaller than an output voltage of the second low voltage terminal, wherein the output voltages of the first and second low voltage terminals are negative values.

11. A signal processing method of output stage circuit comprising:

receiving a first level signal;

maintaining a voltage difference between a gate terminal and a source terminal of a p-type transistor, wherein the voltage difference enables the p-type transistor to work at a linear region when turning on;

outputting a highest system voltage;

receiving a second level signal;

maintaining a voltage difference between a gate terminal and a source terminal of an n-type transistor, wherein the voltage difference enables the n-type transistor to work at a linear region when turning on; and

outputting a lowest system voltage.

12. The signal processing method of output stage circuit of claim 11 , further comprises:

turning off a protection circuit of the p-type transistor, and turning on a protection circuit of the n-type transistor in accordance with the first level signal; and

turning off the protection circuit of the n-type transistor, and turning on the protection circuit of the p-type transistor in accordance with the second level signal.