Clock generation circuit and wireless receiving device
A clock generation circuit includes a random number generator configured to generate random numbers according to a first probability distribution, a filter configured to output random numbers according to a second probability distribution, based on the random numbers according to the first probability distribution input thereto, and a variable delay circuit configured to modulate a clock signal input thereto by delaying edges of the clock signal by amounts corresponding to values of the random numbers according to the second probability distribution. Probability of a smallest number according to the second probability distribution is smaller than probability of the smallest number according to the first probability distribution, and probability of a largest number according to the second probability distribution is smaller than probability of the largest number according to the first probability distribution.
1. A clock generation circuit, comprising:
a random number generator configured to generate random numbers according to a first probability distribution;
a filter configured to output random numbers according to a second probability distribution, based on the random numbers according to the first probability distribution input thereto; and
a variable delay circuit configured to modulate a clock signal input thereto by delaying edges of the clock signal by amounts corresponding to values of the random numbers according to the second probability distribution, wherein
probability of a smallest number according to the second probability distribution is smaller than probability of the smallest number according to the first probability distribution, and probability of a largest number according to the second probability distribution is smaller than probability of the largest number according to the first probability distribution.
2. The clock generation circuit according to claim 1 , wherein
probability of a median number according to the second probability distribution is greater than probability of the median number according to the first probability distribution.
3. The clock generation circuit according to claim 1 , wherein
the first probability distribution is an uniform probability distribution.
4. The clock generation circuit according to claim 1 , wherein
a phase of the clock signal delayed by an amount corresponding to the smallest number is equal to a phase of the clock signal delayed by an amount corresponding to the largest number.
5. The clock generation circuit according to claim 1 , wherein the variable delay circuit includes:
a first inverter to which the clock signal is input;
an RC circuit connected to the first inverter and having a variable register of which resistance is set to values corresponding to the random numbers according to the second probability distribution, and a variable capacitor of which resistance is set to values corresponding to the random numbers according to the second probability distribution; and
a second inverter connected to the RC circuit and output a clock signal modulated by the RC circuit.
6. The clock generation circuit according to claim 1 , wherein the variable delay circuit includes:
a chain of inverters including a first inverter and a last inverter, the first inverter receiving the clock signal, the last inverter providing the modulated clock signal, each inverter having a positive power input and a negative power input;
a first variable resistor connected between a first potential and the positive power inputs of the inverters, resistance thereof being set to values corresponding to the random numbers according to the second probability distribution; and
a second variable resistor connected between a second potential and the negative power inputs of the inverters, resistance thereof being set to values corresponding to the random numbers according to the second probability distribution.
7. The clock generation circuit according to claim 1 , wherein the variable delay circuit includes:
a first chain of inverters;
a second chain of inverters, the second chain having a greater number of inverters than the first chain;
a first switch configured to connect the input clock signal to one of the first chain or the second chain, based on the number output from the filter.
8. The clock generation circuit according to claim 1 , wherein the variable delay circuit includes:
a plurality of inverters arranged in a chain and having a first inverter that receives the input clock signal; and
a selection switch configured to connect an output of one of the inverters to an output terminal od the variable delay circuit.
9. The clock generation circuit according to claim 1 , wherein the random number generator includes:
a starter circuit that receives one of a plurality of starting numbers;
a shift register that includes a plurality of flip-flop stages which generate a number based on said one of the starting numbers; and
a logic circuit that receives the generated number from the shift register, and provide the random numbers having the first probability distribution.
10. The clock generation circuit according to claim 1 , wherein the filter includes:
a delay circuit configured to generate a delayed random number based on each of the random numbers having the first probability distribution; and
a full adder configured to add the delayed random number and a corresponding one of the random numbers having the first probability distribution, and provide the random numbers having the second probability distribution.
11. The clock generation circuit according to claim 1 , wherein the filter includes:
a delay circuit configured to generate a delayed random number based on each of the random numbers having the first probability distribution;
an inverter configured to invert each of the random numbers having the first probability distribution; and
a full adder configured to add the delayed random number and a corresponding one of the inverted random numbers having the first probability distribution, and provide the random numbers having the second probability distribution.
12. A wireless communication device, comprising:
an antenna;
an analog circuit configured to process an analog signal output from the antenna;
a digital circuit configured to process an analog signal output from the analog circuit; and
a clock generation circuit configured to supply a clock signal to the digital circuit, the clock generation circuit including:
a random number generator configured to generate random numbers according to a first probability distribution;
a filter configured to output random numbers according to a second probability distribution, based on the random numbers according to the first probability distribution input thereto; and
a variable delay circuit configured to modulate a clock signal input thereto by delaying edges of the clock signal by amounts corresponding to values of the random numbers according to the second probability distribution and output the modulated clock signal to the digital circuit, wherein
probability of a smallest number according to the second probability distribution is smaller than probability of the smallest number according to the first probability distribution, and probability of a largest number according to the second probability distribution is smaller than probability of the largest number according to the first probability distribution.
13. The wireless communication device according to claim 12 , wherein
probability of a median number according to the second probability distribution is greater than probability of the median number according to the first probability distribution.
14. The wireless communication device according to claim 12 , wherein
the first probability distribution is an uniform probability distribution.
15. The wireless communication device according to claim 12 , wherein
a phase of the clock signal delayed by an amount corresponding to the smallest number is equal to a phase of the clock signal delayed by an amount corresponding to the largest number.
16. A method for modulating a clock signal, comprising:
generating random numbers having a first probability distribution;
generating random numbers having a second probability distribution, based on the random numbers having the first probability distribution; and
delaying edges of a clock signal by amounts corresponding to values of the random numbers according to the second probability distribution, wherein
probability of a smallest number according to the second probability distribution is smaller than probability of the smallest number according to the first probability distribution, and probability of a largest number according to the second probability distribution is smaller than probability of the largest number according to the first probability distribution.
17. The method according to claim 16 , wherein
probability of a median number according to the second probability distribution is greater than probability of the median number according to the first probability distribution.
18. The method according to claim 16 , wherein
the first probability distribution is an uniform probability distribution.
19. The method according to claim 16 , wherein
a phase of the clock signal delayed by an amount corresponding to the smallest number is equal to a phase of the clock signal delayed by an amount corresponding to the largest number.