Connection for quick search of regular expressions in data
The presented connection processes a stream data by a computer. The data is split into blocks called packets and the task is to search for a match of the data in packets with specified patterns—regular expressions, useful in the field of telecommunication technology and services. The connection may be formed within a semiconductor circuit, which serves for receiving, processing, and sending packets. This semiconductor circuit may be implemented by an FPGA-type circuit. In this way, instead of one circuit implementing the automaton with a total data width Sc, a set of simultaneously operating circuits is implemented forming several identical automata at a smaller data width Sn. This eliminates the exponential rise in the number of symbols in the automaton and at the same time it allows achieving a high throughput of the entire connection.
1. A connection for a quick search of regular expressions in data wherein it consists of a the memory write control circuit equipped with the data input with the width S c and data outputs with the data width S n , each of which is connected to the first input of one of N block memories forming a buffer memory, where the total number of block memories is the parameter of the whole solution and is given by the equation N=S c /S n , where S c is the total required data width of the buffer memory and S n is the data width of individual block memories, which is identical for all the block memories, and further the memory write control circuit is equipped with the output connected to the request queue block, while the output of this request queue block is connected to the input of the read control circuit and the reservation output of this read control circuit is connected to the first input of the reservation circuit, while the output of this reservation circuit is interconnected with the input for the memory release of the memory write control circuit, and each block memory has to its second input connected the output of the signals of the read control of the memory management circuit, where to the first input of the memory management circuit of the first block memory is connected the activation output of the read control circuit, and where the memory management circuits are connected in a ring connection such that always the activation output of the preceding memory management circuit is interconnected with the input of the next memory management circuit, while the output of the last memory management circuit is connected to the input of the address incrementation circuit, which is by its first output of processing termination connected to the second input of the reservation circuit, and further the address incrementation circuit is by its second output connected to the second input of the memory management circuit of the first block memory in a ring connection, and the data output of each block memory is connected to the input of the comparator circuit belonging to such block memory, where these comparator circuits are by their outputs of the status signals connected in a ring connection, where the output of the status signal of the comparator circuit of the last block memory is interconnected with the input of the comparator circuit of the first block memory, while the outputs of individual comparator circuits are the outputs of the entire connection.
2. The connection according to claim 1 wherein it is created within a semiconductor circuit.
3. The connection according to claim 2 wherein the semiconductor circuit is an FPGA-type circuit.