System, apparatus, and method for N/P tuning in a fin-FET
The n-type to p-type fin-FET strength ratio in an integrated logic circuit may be tuned by the use of cut regions in the active and dummy gate electrodes. In some examples, separate cut regions for the dummy gate electrodes and the active gate electrode may be used to allow for different lengths of gate pass-active regions resulting in appropriately tuned integrated logic circuits.
1. A fin-FET comprising:
an active gate electrode extending vertically a first distance, the active gate electrode configured to have a first input of a ground potential or a positive voltage potential;
a first dummy gate electrode extending vertically a second distance, the first dummy gate electrode being in parallel with the active gate electrode and configured to have a second input of the ground potential or the positive voltage potential opposite the first input;
a first cut region extending horizontally across the first dummy gate electrode;
a second cut region spaced vertically from the first cut region and extending horizontally across the first dummy gate electrode;
an active region between the first cut region and the second cut region;
a dummy gate pass-active region between the first cut region and the active region along the first dummy gate electrode; and
an active gate pass-active region between an end of the active gate electrode and the active region along the active gate electrode.
2. The fin-FET of claim 1 , wherein the active gate pass-active region is one of approximately 0.326 μm, 0.1 μm, 0.042 μm, or 0.035 μm.
3. The fin-FET of claim 2 , wherein the dummy gate pass-active region is shorter than the active gate pass-active region and is one of approximately 0.326 μm, 0.1 μm, 0.042 μm, or 0.035 μm.
4. The fin-FET of claim 1 , further comprising a second dummy gate electrode extending in parallel with the first dummy gate electrode and spaced horizontally therefrom, the second dummy gate electrode configured to have a third input the same as the second input, wherein the first cut region includes a first portion extending across the second dummy gate electrode and a second portion extending across the first dummy gate electrode, a second dummy gate pass-active region being between the first portion of the first cut region and the active region.
5. The fin-FET of claim 4 , wherein the first portion of the first cut region has a width smaller than a width of the second portion of the first cut region.
6. The fin-FET of claim 4 , wherein the first portion of the first cut region has a width larger than a width of the second portion of the first cut region.
7. The fin-FET of claim 4 , wherein the second cut region includes a first portion extending across the second dummy gate electrode and a second portion extending across the first dummy gate electrode.
8. The fin-FET of claim 7 , further comprising a third dummy gate electrode extending in parallel with the first dummy gate electrode and spaced horizontally therefrom, the third dummy gate electrode configured to have a fourth input; the second portion of the first cut region extending horizontally across the third dummy gate electrode; and the second portion of the second cut region extending horizontally across the third dummy gate electrode.
9. The fin-FET of claim 8 , further comprising a fourth dummy gate electrode extending in parallel with the third dummy gate electrode and spaced horizontally therefrom opposite the active gate electrode, the fourth dummy gate electrode configured to have a fifth input; the first portion of the first cut region extending horizontally across the fourth dummy gate electrode; and the first portion of the second cut region extending horizontally across the fourth dummy gate electrode.
10. The fin-FET of claim 7 , wherein the first portion of the second cut region has a width smaller than a width of the second portion of the second cut region.
11. The fin-FET of claim 7 , wherein the first portion of the second cut region has a width larger than a width of the second portion of the second cut region.
12. The fin-FET of claim 8 , wherein the second portion of the first cut region extends continuously between the first dummy gate electrode and the third dummy gate electrode, the second portion of the second cut region extends continuously between the first dummy gate electrode and the third dummy gate electrode.
13. The fin-FET of claim 1 , wherein the fin-FET is incorporated into a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.
14. A fin-FET comprising:
an active gate electrode extending vertically a first distance, the active gate electrode configured to have a first input of a ground potential or a positive voltage potential;
a first dummy gate electrode extending vertically a second distance, the first dummy gate electrode being in parallel with the active gate electrode and configured to have a second input of the ground potential or the positive voltage potential opposite the first input;
a second dummy gate electrode extending in parallel with the first dummy gate electrode and spaced horizontally therefrom, the second dummy gate electrode configured to have a third input the same as the second input;
a first cut region extending horizontally across the first dummy gate electrode and the second dummy gate electrode;
a second cut region spaced vertically from the first cut region and extending horizontally across the first dummy gate electrode and the second dummy gate electrode;
an active region between the first cut region and the second cut region;
a first dummy gate pass-active region between the first cut region and the active region along the first dummy gate electrode;
a second dummy gate pass-active region between the first cut region and the active region along the second dummy gate electrode; and
an active gate pass-active region between an end of the active gate electrode and the active region along the active gate electrode.
15. The fin-FET of claim 14 , wherein the active gate pass-active region is one of approximately 0.326 μm, 0.1 μm, 0.042 μm, or 0.035 μm.
16. The fin-FET of claim 15 , wherein the first dummy gate pass-active region is shorter than the active gate pass-active region and is one of approximately 0.326 μm, 0.1 μm, 0.042 μm, or 0.035 μm.
17. The fin-FET of claim 16 , wherein the second dummy gate pass-active region is shorter than the active gate pass-active region and is one of approximately 0.326 μm, 0.1 μm, 0.042 μm, or 0.035 μm.
18. The fin-FET of claim 14 , wherein the first cut region includes a first portion extending across the second dummy gate electrode and a second portion extending across the first dummy gate electrode, the second dummy gate pass-active region being between the first portion of the first cut region and the active region, the first portion of the first cut region has a width smaller than a width of the second portion of the first cut region.
19. The fin-FET of claim 14 , wherein the first cut region includes a first portion extending across the second dummy gate electrode and a second portion extending across the first dummy gate electrode, the second dummy gate pass-active region being between the first portion of the first cut region and the active region, the first portion of the first cut region has a width larger than a width of the second portion of the first cut region.
20. The fin-FET of claim 14 , wherein the fin-FET is incorporated into a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.