Method to improve device performance for FinFET

1. A method for manufacturing a semiconductor device, the method comprising:

providing a semiconductor structure comprising:

a substrate structure comprising a semiconductor substrate;

a plurality of fins comprising a semiconductor layer extending into the semiconductor substrate and a first set of fins configured to form a plurality of first type devices; and

a gate structure disposed on the fins;

removing a portion of each of the first set of fins not covered by the gate structure to form a remaining portion of each of the first set of fins;

performing a first epitaxially growth process to form a plurality of first epitaxially grown regions on the remaining portion of each of the first set of fins;

performing a first annealing process so that a volume of a lower portion of each of the first epitaxially grown regions increases and a volume of an upper portion of each of the first epitaxially grown regions decreases, the first epitaxially grown regions being separated from each other before and after the first annealing process;

performing a second epitaxially growth process to form a plurality of second epitaxially grown regions on corresponding annealed first epitaxially grown regions; and

performing a second annealing process so that a volume of a lower portion of each of the second epitaxially grown regions increases and a volume of an upper portion of each of the second epitaxially grown regions decreases, the second epitaxially grown regions being separated from each other before and after the second annealing process.

2. The method of claim 1 , wherein the substrate structure comprises an insulating layer on the semiconductor substrate, and the fins protrude from the insulating layer.

3. The method of claim 1 , wherein removing the portion of each of the fins comprises:

forming a patterned mask exposing the portion of the fins not covered by the gate structure; and

removing the exposed portion by etching using the patterned mask as a mask.

4. The method of claim 1 , wherein the first annealing process is performed in situ in a hydrogen atmosphere, at a temperature in a range between 700° C. and 800° C., and a time period in a range between 5 minutes and 30 minutes.

5. The method of claim 1 , wherein the second annealing process is performed in situ in a hydrogen atmosphere, at a temperature in a range between 700° C. and 800° C., and a time period in a range between 5 minutes and 30 minutes.

6. The method of claim 1 , wherein the plurality of fins further comprise a second set of fins configured to form a plurality of second type devices, the method further comprising, prior to removing the portion of each of the first set of fins:

forming a first barrier layer on the semiconductor structure; and

removing a portion of the first barrier layer disposed on the first set of fins to expose the portion of the first set of fins not covered by the gate structure.

7. The method of claim 6 , further comprising, after performing the second annealing process:

forming a second barrier layer on the second epitaxially grown regions;

removing a portion of the first barrier layer on the second set of fins exposing a portion of the second set of fins that is not covered by the gate structure;

removing the exposed portion of the second set of fins that is not covered by the gate structure to form a remaining portion of each of the second set of fins;

performing a third epitaxially growth process to form a plurality of third epitaxially grown regions on the remaining portion of each of the second set of fins;

performing a third annealing process so that a volume of a lower portion of each of the third epitaxially grown regions increases and a volume of an upper portion of each of the third epitaxially grown regions decreases, the third epitaxially grown regions being separated from each other before and after the third annealing process;

performing a fourth epitaxially growth process to form a plurality of fourth epitaxially grown regions on corresponding annealed third epitaxially grown regions; and

performing a fourth annealing process so that a volume of a lower portion of each of the fourth epitaxially grown regions increases and a volume of an upper portion of each of the fourth epitaxially grown regions decreases, the fourth epitaxially grown regions being separated from each other before and after the fourth annealing process.

8. The method of claim 7 , the third annealing process is performed in situ in a hydrogen atmosphere, at a temperature in a range between 700° C. and 800° C., and a time period in a range between 5 minutes and 30 minutes.

9. The method of claim 7 , the fourth annealing process is performed in situ in a hydrogen atmosphere, at a temperature in a range between 700° C. and 800° C., and a time period in a range between 5 minutes and 30 minutes.

10. The method of claim 1 , wherein the semiconductor layer of the fins is silicon, and the first epitaxially grown regions comprise SiGe or SiP.

11. A semiconductor device comprising:

a semiconductor structure comprising:

a substrate structure including a semiconductor substrate;

a plurality of fins including a semiconductor layer extending into the semiconductor substrate, a first set of fins configured to form a plurality of first type devices, and a second set of fins configured to form a plurality of second type devices; and

a gate structure disposed on the fins;

a plurality of first epitaxially grown regions each disposed on one of the first set of fins, the first epitaxially grown regions being separated from each other; and a volume of a lower portion of each of the first epitaxially grown regions is greater than a volume of an upper portion of each of the first epitaxially grown regions, and the upper portion of each of the first epitaxially grown regions has a curved surface;

a plurality of second epitaxially grown regions each disposed on one of the second set of fins, the second epitaxially grown regions being separated from each other; and a volume of a lower portion of each of the second epitaxially grown regions is greater than a volume of an upper portion of each of the second epitaxially grown regions; and

a first barrier layer having a first height on side surfaces of the first set of fins and a second height on side surfaces of the second set of fins, the first height being different from the second height.

12. The semiconductor device of claim 11 , wherein the semiconductor layer of the fins is silicon, and the first epitaxially grown regions comprise SiGe or SiP.

13. The semiconductor device of claim 11 , wherein the upper portion of each of the second epitaxially grown regions has a curved surface.

14. The semiconductor device of claim 11 , wherein a height of the first epitaxially grown regions is different from a height of the second epitaxially grown regions.

15. The semiconductor device of claim 11 , wherein each of the second epitaxially grown regions has a fingertip or strawberry cross-sectional shape.

16. The semiconductor device of claim 11 , further comprising:

a second barrier layer overlying the lower portion of each of the first epitaxially grown regions.

17. The semiconductor device of claim 11 , wherein each of the first epitaxially grown regions has a fingertip or strawberry cross-sectional shape.

18. The semiconductor device of claim 11 , wherein the first type devices are PMOS transistor devices, and the second type devices are NMOS transistor devices.

19. The semiconductor device of claim 11 , further comprising an interlayer dielectric layer on the semiconductor structure.

20. The semiconductor device of claim 19 , further comprising a contact electrode disposed in the interlayer dielectric layer and having electrical contact with the first and second epitaxially grown regions.