IP Library Granted Patent US 9,978,774
Granted Patent B2
US 9,978,774 · App. 15/420,628 · Granted May 22, 2018

Semiconductor device and method for manufacturing the same

Inventors: Shunpei Yamazaki (Tokyo, JP); Yuta Endo (Kanagawa, JP); Kiyoshi Kato (Kanagawa, JP); Satoru Okamoto (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/1207H01L21/0214H01L21/0228H01L21/02178H01L21/02183H01L21/02266H01L21/02271H01L21/76825H01L21/76834H01L23/528H01L23/53295H01L27/1052H01L29/24H01L29/66969H01L29/7869
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Quick Facts
Patent No.
US 9,978,774
App. No.
15/420,628
Granted
May 22, 2018
Kind
B2
Abstract

A highly reliable semiconductor device suitable for miniaturization and high integration is provided. The semiconductor device includes a first insulator; a transistor over the first insulator; a second insulator over the transistor; a first conductor embedded in an opening in the second insulator; a barrier layer over the first conductor; a third insulator over the second insulator and over the barrier layer; and a second conductor over the third insulator. The first insulator, the third insulator, and the barrier layer have a barrier property against oxygen and hydrogen. The second insulator includes an excess-oxygen region. The transistor includes an oxide semiconductor. The barrier layer, the third insulator, and the second conductor function as a capacitor.

Claims (18)

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first insulator over a first transistor, a channel formation region of the first transistor comprising part of a semiconductor substrate;

forming a second transistor over the first insulator, a channel formation region of the second transistor comprising an oxide semiconductor;

forming a second insulator over the second transistor;

forming an opening in the second insulator, the opening reaching the second transistor;

forming a first conductor over the second insulator to embed the first conductor in the opening of the second insulator;

removing part of the first conductor to expose a top surface of the second insulator;

forming a barrier layer over the first conductor;

performing oxygen plasma treatment on the barrier layer and the second insulator;

forming a third insulator over the barrier layer and the second insulator; and

forming a second conductor over the third insulator,

wherein the barrier layer, the third insulator, and the second conductor overlap with each other and function as a capacitor, and

wherein each of the first insulator, the barrier layer, and the third insulator has a barrier property against oxygen and hydrogen.

2. The method for manufacturing the semiconductor device according to claim 1 , wherein the second insulator comprises silicon oxynitride formed by a CVD method.

3. The method for manufacturing the semiconductor device according to claim 1 , wherein the barrier layer comprises tantalum nitride formed by an ALD method.

4. The method for manufacturing the semiconductor device according to claim 1 , wherein the barrier layer comprises aluminum oxide formed by an ALD method.

5. The method for manufacturing the semiconductor device according to claim 1 , wherein the third insulator comprises aluminum oxide formed by a sputtering method.

6. The method for manufacturing the semiconductor device according to claim 1 , wherein an impurity included in the second insulator is removed by the oxygen plasma treatment.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 23, 2017
From: YAMAZAKI, SHUNPEI; ENDO, YUTA; KATO, KIYOSHI; OKAMOTO, SATORU
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 041711/0573 →
Priority Claims (1)
JP 2016-024794 · Feb 12, 2016 · national
Continuity (1)
Related Publication 20170236839A1 · Aug 17, 2017