Semiconductor device
To improve the performance of a semiconductor device having an IGBT. A p + -type collector layer is formed on the back surface side of a semiconductor substrate. A back electrode is formed over the back surface of the semiconductor substrate. Within the semiconductor substrate, an n − -type drift region is formed over the p + -type collector layer, and a first IGBT cell region and a second IGBT cell region are formed on the surface side of the semiconductor substrate. An embedded insulating film is formed on the surface side of the semiconductor substrate between the first IGBT cell region and the second IGBT cell region. An interlayer insulating film is formed over the first IGBT cell region, the second IGBT cell region, and the embedded insulating film. An emitter electrode is formed over the interlayer insulating film.
1. A semiconductor device equipped with an Insulated Gate Bipolar Transistor (IGBT), the semiconductor device comprising:
a semiconductor substrate having a first main surface and a second main surface on a side opposite to a side of the first main surface;
a collector region of a first conductivity type formed on the second main surface side within the semiconductor substrate;
a collector electrode formed over the second main surface of the semiconductor substrate and electrically coupled to the collector region;
a drift region of a second conductivity type opposite to the first conductivity type, which is formed over the collector region within the semiconductor substrate;
a first IGBT cell region and a second IGBT cell region formed on the first main surface side of the semiconductor substrate and disposed apart from each other in a first direction in a plan view;
an embedded insulating film formed on the first main surface side of the semiconductor substrate and disposed between the first IGBT cell region and the second IGBT cell region in the plan view;
an interlayer insulating film formed over the first IGBT cell region, the second IGBT cell region, and the embedded insulating film; and
an emitter electrode formed over the interlayer insulting film,
wherein, in the first direction, a width of the embedded insulating film is greater than a width of the first IGBT cell region and a width of the second IGBT cell region.
2. The semiconductor device according to claim 1 , wherein the first main surface of the semiconductor substrate in the first IGBT cell region, the first main surface of the semiconductor substrate in the second IGBT cell region, and an upper surface of the embedded insulating film are at a same height.
3. The semiconductor device according to claim 1 , wherein an upper surface of the interlayer insulating film is flat above the embedded insulating film.
4. The semiconductor device according to claim 3 , wherein a lower surface of the emitter electrode is flat above the embedded insulating film.
5. The semiconductor device according to claim 1 , wherein the embedded insulating film and the interlayer insulting film are interposed between the emitter electrode to be a portion positioned above the embedded insulating film and the semiconductor substrate to be a portion positioned below the embedded insulating film.
6. The semiconductor device according to claim 1 , further comprising a gate electrode formed over the interlayer insulating film,
wherein the first IGBT cell region includes:
a first trench formed on the first main surface side of the semiconductor substrate and extending in a second direction crossing the first direction in the plan view;
a second trench and a third trench formed on the first main surface side of the semiconductor substrate, disposed on both sides with the first trench interposed therebetween, and extending in the second direction in the plan view;
a first trench gate electrode formed within the first trench through a first insulating film;
a first trench electrode formed within the second trench through a second insulating film; and
a second trench electrode formed within the third trench through a third insulating film,
wherein the second IGBT cell region includes:
a fourth trench formed on the first main surface side of the semiconductor substrate and extending in the second direction in the plan view;
a fifth trench and a sixth trench formed on the first main surface side of the semiconductor substrate, disposed on both sides with the fourth trench interposed therebetween, and extending in the second direction in the plan view;
a second trench gate electrode formed within the fourth trench through a fourth insulating film;
a third trench electrode formed within the fifth trench through a fifth insulating film; and
a fourth trench electrode formed within the sixth trench through a sixth insulating film,
wherein the first trench electrode, the second trench electrode, the third trench electrode, and the fourth trench electrode are electrically coupled to the emitter electrode,
wherein the first trench gate electrode and the second trench gate electrode are electrically coupled to the gate electrode, and
wherein the embedded insulating film is adjacent to the second trench in the first IGBT cell region in the first direction and adjacent to the sixth trench in the second IGBT cell region in the first direction.
7. The semiconductor device according to claim 6 , wherein a substrate region comprised of the semiconductor substrate is not interposed between the embedded insulating film and the second trench electrode and between the embedded insulating film and the fourth trench electrode.
8. The semiconductor device according to claim 6 , wherein, in the semiconductor substrate, a first semiconductor region of the first conductivity type is formed below the embedded insulating film to be adjacent to the embedded insulating film, and
wherein a bottom face of the second trench and a bottom face of the sixth trench are covered with the first semiconductor region.
9. The semiconductor device according to claim 8 , wherein the drift region exists below the first semiconductor region.
10. The semiconductor device according to claim 6 , wherein the first IGBT cell region further includes:
a first channel forming region of the first conductivity type formed on the first main surface side in the semiconductor substrate to be a portion interposed between the first trench and the second trench;
a first emitter region of the second conductivity type formed at an upper portion of the first channel forming region and at a position adjacent to the first trench in the semiconductor substrate to be the portion interposed between the first trench and the second trench;
a second channel forming region of the first conductivity type formed on the first main surface side in the semiconductor substrate to be a portion interposed between the first trench and the third trench; and
a second emitter region of the second conductivity type formed at an upper portion of the second channel forming region and at a position adjacent to the first trench in the semiconductor substrate to be the portion interposed between the first trench and the third trench, and
wherein the second IGBT cell region further includes:
a third channel forming region of the first conductivity type formed on the first main surface side in the semiconductor substrate to be a portion interposed between the fourth trench and the fifth trench;
a third emitter region of the second conductivity type formed at an upper portion of the third channel forming region and at a position adjacent to the fourth trench in the semiconductor substrate to be the portion interposed between the fourth trench and the fifth trench;
a fourth channel forming region of the first conductivity type formed on the first main surface side in the semiconductor substrate to be a portion interposed between the fourth trench and the sixth trench; and
a fourth emitter region of the second conductivity type formed at an upper portion of the fourth channel forming region and at a position adjacent to the fourth trench in the semiconductor substrate to be the portion interposed between the fourth trench and the sixth trench.
11. The semiconductor device according to claim 10 , further comprising:
a first contact trench which penetrates through the interlayer insulating film and is formed by digging in a part of the semiconductor substrate to be the portion interposed between the first trench and the second trench;
a first coupling electrode embedded into the first contact trench;
a second contact trench which penetrates through the interlayer insulating film and is formed by digging in a part of the semiconductor substrate to be the portion interposed between the first trench and the third trench;
a second coupling electrode embedded into the second contact trench;
a third contact trench which penetrates through the interlayer insulating film and is formed by digging in a part of the semiconductor substrate to be the portion interposed between the fourth trench and the fifth trench;
a third coupling electrode embedded into the third contact trench;
a fourth contact trench which penetrates through the interlayer insulating film and is formed by digging in a part of the semiconductor substrate to be the portion interposed between the fourth trench and the sixth trench; and
a fourth coupling electrode embedded into the fourth contact trench,
wherein the first coupling electrode is electrically coupled to the first channel forming region and the first emitter region and electrically coupled to the emitter electrode,
wherein the second coupling electrode is electrically coupled to the second channel forming region and the second emitter region and electrically coupled to the emitter electrode,
wherein the third coupling electrode is electrically coupled to the third channel forming region and the third emitter region and electrically coupled to the emitter electrode, and
wherein the fourth coupling electrode is electrically coupled to the fourth channel forming region and the fourth emitter region and electrically coupled to the emitter electrode.
12. The semiconductor device according to claim 11 , wherein the first coupling electrode, the second coupling electrode, the third coupling electrode, and the fourth coupling electrode are formed integrally with the emitter electrode.
13. The semiconductor device according to claim 11 , wherein the first IGBT cell region further includes:
a first hole barrier region of the second conductivity type formed below the first channel forming region in the semiconductor substrate to be the portion interposed between the first trench and the second trench; and
a second hole barrier region of the second conductivity type formed below the second channel forming region in the semiconductor substrate to be the portion interposed between the first trench and the third trench,
wherein the second IGBT cell region further includes:
a third hole barrier region of the second conductivity type formed below the third channel forming region in the semiconductor substrate to be the portion interposed between the fourth trench and the fifth trench; and
a fourth hole barrier region of the second conductivity type formed below the fourth channel forming region in the semiconductor substrate to be the portion interposed between the fourth trench and the sixth trench,
wherein the drift region exists below the first hole barrier region, the second hole barrier region, the third hole barrier region, and the fourth hole barrier region, and
wherein the first hole barrier region, the second hole barrier region, the third hole barrier region, and the fourth hole barrier region are respectively higher in impurity concentration than the drift region.
14. The semiconductor device according to claim 6 , wherein a depth of a bottom face of the embedded insulating film is not deeper than a depth of each of the bottom faces of the second and sixth trenches.
15. The semiconductor device according to claim 14 , wherein a difference between the depth of the bottom face of the embedded insulating film and the depth of each of the bottom faces of the second and sixth trenches is less than or equal to 1/10 of a thickness of the embedded insulating film.
16. The semiconductor device according to claim 6 , wherein the depth of the bottom face of the embedded insulating film is the same as the depth of each of the bottom faces of the second and sixth trenches.
17. A semiconductor device equipped with an Insulated Gate Bipolar Transistor (IGBT), the semiconductor device comprising:
a semiconductor substrate having a first main surface and a second main surface on a side opposite to a side of the first main surface;
a collector region of a first conductivity type formed on the second main surface side within the semiconductor substrate;
a collector electrode formed over the second main surface of the semiconductor substrate and electrically coupled to the collector region;
a drift region of a second conductivity type opposite to the first conductivity type, which is formed over the collector region within the semiconductor substrate;
a first IGBT cell region and a second IGBT cell region formed on the first main surface side of the semiconductor substrate and disposed apart from each other in a first direction in a plan view;
an embedded insulating film formed on the first main surface side of the semiconductor substrate and disposed between the first IGBT cell region and the second IGBT cell region in the plan view;
an interlayer insulating film formed over the first IGBT cell region, the second IGBT cell region, and the embedded insulating film; and
an emitter electrode and a gate electrode formed over the interlayer insulting film,
wherein the first IGBT cell region includes:
a first trench formed on the first main surface side of the semiconductor substrate and extending in a second direction crossing the first direction in the plan view;
a second trench and a third trench formed on the first main surface side of the semiconductor substrate, disposed on both sides with the first trench interposed therebetween, and extending in the second direction in the plan view;
a first trench gate electrode formed within the first trench through a first insulating film;
a first trench electrode formed within the second trench through a second insulating film; and
a second trench electrode formed within the third trench through a third insulating film,
wherein the second IGBT cell region includes:
a fourth trench formed on the first main surface side of the semiconductor substrate and extending in the second direction in the plan view;
a fifth trench and a sixth trench formed on the first main surface side of the semiconductor substrate, disposed on both sides with the fourth trench interposed therebetween, and extending in the second direction in the plan view;
a second trench gate electrode formed within the fourth trench through a fourth insulating film;
a third trench electrode formed within the fifth trench through a fifth insulating film; and
a fourth trench electrode formed within the sixth trench through a sixth insulating film,
wherein the first trench electrode, the second trench electrode, the third trench electrode, and the fourth trench electrode are electrically coupled to the emitter electrode,
wherein the first trench gate electrode and the second trench gate electrode are electrically coupled to the gate electrode,
wherein the embedded insulating film is adjacent to the second trench in the first IGBT cell region in the first direction and adjacent to the sixth trench in the second IGBT cell region in the first direction,
wherein in the semiconductor substrate, a first semiconductor region of the first conductivity type is formed below the embedded insulating film to be adjacent to the embedded insulating film, and
wherein a bottom face of the second trench and a bottom face of the sixth trench are covered with the first semiconductor region.
18. The semiconductor device according to claim 1 , further comprising a gate electrode formed over the interlayer insulating film,
wherein the first IGBT cell region includes:
a first trench formed on the first main surface side of the semiconductor substrate and extending in a second direction crossing the first direction in the plan view; and
a second trench and a third trench formed on the first main surface side of the semiconductor substrate, disposed on both sides with the first trench interposed therebetween, and extending in the second direction in the plan view.
19. The semiconductor device according to claim 18 , wherein the first IGBT cell region further includes:
a first trench gate electrode formed within the first trench through a first insulating film;
a first trench electrode formed within the second trench through a second insulating film; and
a second trench electrode formed within the third trench through a third insulating film.
20. The semiconductor device according to claim 19 , wherein the second IGBT cell region includes:
a fourth trench formed on the first main surface side of the semiconductor substrate and extending in the second direction in the plan view; and
a fifth trench and a sixth trench formed on the first main surface side of the semiconductor substrate, disposed on both sides with the fourth trench interposed therebetween, and extending in the second direction in the plan view.