Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a substrate, a first semiconductor fin, a second semiconductor fin, and a first lightly-doped drain (LDD) region. The first semiconductor fin is disposed on the substrate. The first semiconductor fin has a top surface and sidewalls. The second semiconductor fin is disposed on the substrate. The first semiconductor fin and the second semiconductor fin are separated from each other at a nanoscale distance. The first lightly-doped drain (LDD) region is disposed at least in the top surface and the sidewalls of the first semiconductor fin.
1. A method for manufacturing a semiconductor structure, the method comprising:
forming at least one semiconductor fin on a substrate, wherein the semiconductor fin has a top surface and sidewalls;
forming at least one dielectric layer on the top surface and the sidewalls of the semiconductor fin;
forming a dopant-rich layer comprising at least one impurity on the dielectric layer; and
driving the impurity into the semiconductor fin through the dielectric layer by performing a knock-on implantation to knock the impurity into the dielectric layer.
2. The method of claim 1 , wherein the knock-on implantation is performed using at least one inert-gas ion.
3. The method of claim 1 , further comprising:
implanting at least one diffusion enhancement dopant into the dielectric layer before the driving, wherein the diffusion enhancement dopant is able to enhance the diffusion of the impurity in the dielectric layer.
4. The method of claim 3 , wherein the diffusion enhancement dopant is fluorine.
5. The method of claim 1 , wherein the driving comprises:
performing an annealing process to drive the impurity into the semiconductor fin.
6. The method of claim 5 , further comprising:
forming a cap layer on the dopant-rich layer before the annealing process.
7. The method of claim 5 , wherein the annealing process is performed in an O 2 ambient.
8. The method of claim 1 , wherein the forming the dielectric layer comprises:
forming a gate dielectric layer on the top surface and the sidewalls of the semiconductor fin.
9. The method of claim 1 , wherein the forming the dielectric layer comprises:
forming a seal spacer at least on the top surface and the sidewalls of the semiconductor fin.
10. The method of claim 1 , wherein the dopant-rich layer is formed by plasma ion assisted deposition (PIAD).
11. The method of claim 1 , wherein the sidewalls of the semiconductor fin include upper surfaces adjacent the top surface, and further comprising:
driving the impurity into the top surface and the upper surfaces of the sidewalls semiconductor fin through the dielectric layer.
12. A method of manufacturing a semiconductor structure, the method comprising:
forming a first semiconductor fin and a second semiconductor fin over a substrate, wherein the first semiconductor fin has a top surface and sidewalls and wherein the first semiconductor fin and the second semiconductor fin are separated from each other at a nanoscale distance; and
forming a first lightly-doped drain (LDD) region disposed at least in the top surface and the sidewalls of the first semiconductor fin, wherein the forming the first lightly-doped drain (LDD) region is performed at least in part using a knock-on implantation process; and
forming a seal spacer overlying at least the first lightly-doped drain (LDD) region.
13. The method of claim 12 , wherein the first lightly-doped drain (LDD) region and the seal spacer are doped with substantially the same type impurities.
14. The method of claim 12 , further comprising:
forming a gate dielectric layer overlying at least the first lightly-doped drain (LDD) region.
15. The method of claim 14 , wherein the first lightly-doped drain (LDD) region and the gate dielectric layer are doped with substantially the same type impurities.
16. The method of claim 12 , wherein the second semiconductor fin has a top surface and sidewalls; and
further comprising:
forming a second lightly-doped drain (LDD) region disposed at least in the top surface and the sidewalls of the second semiconductor fin, wherein the first LDD region and the second LDD region are doped with different type impurities.
17. A method for manufacturing a semiconductor structure, the method comprising:
forming at least one semiconductor fin on a substrate, wherein the semiconductor fin has a top surface and sidewalls;
forming at least one dielectric layer on the top surface and the sidewalls of the semiconductor fin;
forming a dielectric seal spacer layer over the at least one dielectric layer;
forming a dopant-rich layer comprising at least one impurity on the dielectric seal spacer layer; and
driving the impurity into the semiconductor fin through the dielectric seal spacer layer and the dielectric layer.
18. The method for manufacturing a semiconductor structure of claim 17 , further including a knock-in implantation to drive the impurity into the dielectric seal spacer layer and the dielectric layer.
19. The method for manufacturing a semiconductor structure of claim 17 , further comprising a drive-in anneal process.
20. The method for manufacturing a semiconductor structure of claim 17 , further comprising implanting a diffusion enhancement dopant into the dielectric layer.